scholarly journals Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

2021 ◽  
Vol 9 (12) ◽  
pp. 862-864
Author(s):  
Mutyala Sri Anantha Lakshmi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Description Language ◽  
Delay Reduction ◽  
Low Area ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Area Reduction ◽  
Hardware Description ◽  
Very High

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

scholarly journals Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor

2020 ◽  
Vol 10 (2) ◽  
pp. 1722
Author(s):  
R. Palanisamy ◽  
C. S. Boopathi ◽  
K. Selvakumar ◽  
K. Vijayakumar
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Dynamic Environment ◽  
Boost Converter ◽  
Pulse Generation ◽  
Description Language ◽  
Course Of Action ◽  
Hardware Description ◽  
Complex Circuits ◽  
Very High

This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

Design of Control Module for Serial DAC Based on FPGA

2013 ◽  
Vol 765-767 ◽  
pp. 2456-2459
Author(s):  
Cai Hong Liu ◽  
Jin Shui Ji ◽  
Ai Qin Qi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
State Transition ◽  
Control Method ◽  
Description Language ◽  
Transition Diagram ◽  
State Transition Diagram ◽  
Timing Diagram ◽  
Hardware Description ◽  
Very High

In order to increase the flexibility of control for serial DAC, a new control method for DAC based on FPGA is proposed in this paper. A state transition diagram can be drawn according to the timing diagram of DAC, Which can be realized in FPGA using Very High-speed Integrated Circuit Hardware Description Language. The simulate results show that logic in FPGA is consistent with the requirements. The module based on FPGA can be modified just by modifying software, not the hardware.

scholarly journals Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor

2019 ◽  
Vol 8 (2) ◽  
pp. 81
Author(s):  
R. Palanisamy ◽  
K. Vijayakumar
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Dynamic Environment ◽  
Boost Converter ◽  
Pulse Generation ◽  
Description Language ◽  
Course Of Action ◽  
Hardware Description ◽  
Complex Circuits ◽  
Very High

<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.</p>

scholarly journals Aes Modes of Operation

2019 ◽  
Vol 8 (9) ◽  
pp. 2213-2217
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Hardware Description Language ◽  
Shopping Malls ◽  
Description Language ◽  
Huge Amount ◽  
Confidential Data ◽  
Hardware Description ◽  
Money Transfers ◽  
Very High

Cryptography is the science of secret codes. Previously we used DES algorithms in order to secure but cannot encrypt completely. Thus, we referred AES Algorithms to create a ciphertext in encryption and is given as an input in decryption. In present scenario, everyone sharing their data in online using internet alsoonline transactions like e-banking for money transfers, in shopping malls, restaurants, and many more. While transferring a huge amount or any confidential data there are many chances to hack the data.There are different modes of operations used in AES in accordance with the efficiency to blur the data. The design has been done in VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and simulated and synthesized using Xilinx.

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