0.3-V $RC$ -to-Digital Converter Using a Negative Charge-Pump Switch

2020 ◽  
Vol 67 (2) ◽  
pp. 245-249 ◽  
Author(s):  
Ki-Chan Woo ◽  
Byung-Do Yang
Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.


2017 ◽  
Vol E100.C (6) ◽  
pp. 548-559
Author(s):  
Anugerah FIRDAUZI ◽  
Zule XU ◽  
Masaya MIYAHARA ◽  
Akira MATSUZAWA

2009 ◽  
Vol 6 (6) ◽  
pp. 304-309 ◽  
Author(s):  
Ji-Hye Bong ◽  
Yong-Jin Kwon ◽  
Daejeong Kim ◽  
Kyeong-Sik Min

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