A high speed and low voltage BiCMOS tristate buffer with positive and negative charge pump

2002 ◽  
Author(s):  
C. Suriyaammaranon ◽  
K. Dejhan ◽  
F. Cheevasuvit ◽  
C. Soonyeekan
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Charge Pump

scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

A New High-Speed Low-Voltage Charge Pump for PLL Applications

2006 ◽  
Author(s):  
Hong Yu ◽  
Y. Inoue ◽  
Yan Han
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Charge Pump

A Fully-On-Chip Analog Low-Dropout Regulator With Negative Charge Pump for Low-Voltage Applications

2019 ◽  
Vol 66 (8) ◽  
pp. 1361-1365 ◽  
Author(s):  
Yi Tan ◽  
Chenchang Zhan ◽  
Guanhua Wang
Keyword(s):  
Negative Charge ◽  
Low Voltage ◽  
Charge Pump ◽  
Low Dropout Regulator ◽  
On Chip

A novel low voltage and high speed CMOS charge pump circuit

2010 ◽  
Author(s):  
Fan Qiang ◽  
Fu Xiansong ◽  
Niu Pingjuan ◽  
Yang Guanghua ◽  
Gao Tiecheng
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Charge Pump ◽  
Charge Pump Circuit

scholarly journals Asymmetric Ge/SiGe coupled quantum well modulators

Nanophotonics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 1765-1773
Author(s):  
Yi Zhang ◽  
Jianfeng Gao ◽  
Senbiao Qin ◽  
Ming Cheng ◽  
Kang Wang ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Quantum Well ◽  
Quantum Wells ◽  
High Speed ◽  
Low Voltage ◽  
Extinction Ratio ◽  
High Frequency Response ◽  
Modulation Format ◽  
Silicon Photonic ◽  
Coupled Quantum Well

Abstract We design and demonstrate an asymmetric Ge/SiGe coupled quantum well (CQW) waveguide modulator for both intensity and phase modulation with a low bias voltage in silicon photonic integration. The asymmetric CQWs consisting of two quantum wells with different widths are employed as the active region to enhance the electro-optical characteristics of the device by controlling the coupling of the wave functions. The fabricated device can realize 5 dB extinction ratio at 1446 nm and 1.4 × 10−3 electrorefractive index variation at 1530 nm with the associated modulation efficiency V π L π of 0.055 V cm under 1 V reverse bias. The 3 dB bandwidth for high frequency response is 27 GHz under 1 V bias and the energy consumption per bit is less than 100 fJ/bit. The proposed device offers a pathway towards a low voltage, low energy consumption, high speed and compact modulator for silicon photonic integrated devices, as well as opens possibilities for achieving advanced modulation format in a more compact and simple frame.

scholarly journals Reliability-Oriented Design of Inverter-Fed Low-Voltage Electrical Machines: Potential Solutions

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4144
Author(s):  
Yatai Ji ◽  
Paolo Giangrande ◽  
Vincenzo Madonna ◽  
Weiduo Zhao ◽  
Michael Galea
Keyword(s):  
Power Density ◽  
High Speed ◽  
High Performance ◽  
Low Voltage ◽  
Electrical Machines ◽  
Design Stage ◽  
Switching Frequency ◽  
Special Focus ◽  
Electrical Machine ◽  
Engineering Approach

Transportation electrification has kept pushing low-voltage inverter-fed electrical machines to reach a higher power density while guaranteeing appropriate reliability levels. Methods commonly adopted to boost power density (i.e., higher current density, faster switching frequency for high speed, and higher DC link voltage) will unavoidably increase the stress to the insulation system which leads to a decrease in reliability. Thus, a trade-off is required between power density and reliability during the machine design. Currently, it is a challenging task to evaluate reliability during the design stage and the over-engineering approach is applied. To solve this problem, physics of failure (POF) is introduced and its feasibility for electrical machine (EM) design is discussed through reviewing past work on insulation investigation. Then the special focus is given to partial discharge (PD) whose occurrence means the end-of-life of low-voltage EMs. The PD-free design methodology based on understanding the physics of PD is presented to substitute the over-engineering approach. Finally, a comprehensive reliability-oriented design (ROD) approach adopting POF and PD-free design strategy is given as a potential solution for reliable and high-performance inverter-fed low-voltage EM design.

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