NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

2002 ◽  
Vol 2 (1) ◽  
pp. 2-8 ◽  
Author(s):  
A. Salman ◽  
R. Gauthier ◽  
W. Stadler ◽  
K. Esmark ◽  
M. Muhammad ◽  
...  
2020 ◽  
Vol 6 (39) ◽  
pp. eabb3755
Author(s):  
Su Xu ◽  
Fu-Yan Dong ◽  
Wen-Rui Guo ◽  
Dong-Dong Han ◽  
Chao Qian ◽  
...  

As a superior self-protection strategy, invisibility has been a topic of long-standing interest in both academia and industry, because of its potential for intriguing applications that have only appeared thus far in science fiction. However, due to the strong dispersion of passive materials, achieving cross-wavelength invisibility remains an open challenge. Inspired by the natural ecological relationship between transparent midwater oceanic animals and the cross-wavelength detection strategy of their predators, we propose a cross-wavelength invisibility concept that integrates various invisibility tactics, where a Boolean metamaterial design procedure is presented to balance divergent material requirements over cross-scale wavelengths. As proof of concept, we experimentally demonstrate longwave cloaking and shortwave transparency simultaneously through a nanoimprinting technique. Our work extends the concept of stealth techniques from individual invisibility tactics targeting a single-wavelength spectrum to an integrated invisibility tactic targeting a cross-wavelength applications and may pave the way for development of cross-wavelength integrated metadevices.


2010 ◽  
Vol 5 (1) ◽  
pp. 7-15
Author(s):  
Matías Miguez ◽  
Joel Gak ◽  
Alfredo Arnaud

An integrated switch to control electrical stimuli in implantable medical devices is presented. First a self-biased protection mechanism to avoid VGS reaching maximum rated value is presented. Then, using a HV-CMOS technology this technique is incorporated in a fully integrated switch, to control 0 to 16V, and 0 to 30 mA, pulses for implantable stimulators. Because of the low supply voltage VDD between 2 to 5V, and safety considerations in implantable devices, special level shifters, drivers, and a voltage multiplier, that drive a large 40000μm/3μm dual-in-series PMOS switch, were necessary for the circuit. The circuit was fabricated in a HV 0.6μm CMOS technology in SOI wafer for transistor isolation, and tested. Measurement results that closely fit the expected performance of the circuit are presented.


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