Medium-Voltage 12-Pulse Converter: Output Voltage Harmonic Compensation Using a Series APF

2014 ◽  
Vol 61 (1) ◽  
pp. 43-52 ◽  
Author(s):  
Mostafa S. Hamad ◽  
Mahmoud I. Masoud ◽  
Barry W. Williams
Energies ◽  
2019 ◽  
Vol 12 (12) ◽  
pp. 2338 ◽  
Author(s):  
Wang ◽  
Zhang ◽  
Song ◽  
Cao

Owing to the necessity of the transformer for the multi-parallel inverters connected to the medium-voltage (MV) grid, the conventional multi-parallel inverter topology can be reconfigured to the dual-inverter fed open-end winding transformer (DI-OEWT) topology to obtain lower output voltage harmonics, which can reduce the requirement of the filter inductance. However, due to the special structure of the DI-OEWT topology, the arrangement scheme of the filter can be more than one kind, and different schemes may affect the filter performance. In this paper, research on the existing two kinds of filters, as well as a proposed one, for the DI-OEWT topology used in photovoltaic grid-tied applications is presented. The equivalent circuits of these filters are derived, and based on this, the harmonic suppression capability of these filters is analyzed and compared. Furthermore, a brief parameter design method of these filters is also introduced, and based on the design examples, the inductance and capacitance requirements of these filters are compared. In addition, these filters are also evaluated in terms of the applicability for fault tolerance. At last, the analysis is verified through an experiment on a 30 kW dual-three-level inverter prototype.


2021 ◽  
Author(s):  
Arifur Rahman Shohel

This project focuses on the topology of multilevel neutral point clamped (NPC)/H-bridge inverters and their modified modulation technique for high-power (megawatts) medium voltage (typically 6000 v) applications. A sinusodial pulse width in-phase disposition modulation is proposed for five-level NPC/H-bridge inverters. The inverter achieves good harmonic performance and low dv/dt in its output voltage waveforms in comparison to the conventional three-level NPC inverter. A seven-level NPC/H-bridge topology and its sinusodial pulse width in-phase disposition modulation are also proposed and investigated, which has better performance than the five-level inverters. Theoretical analysis and computer simulation are carried out for the proposed inverter topologies and algorithms. The output voltage waveforms and harmonic performance are verified by experiments on a five-level NPC/H-bridge inverters.


2019 ◽  
Vol 28 (04) ◽  
pp. 1950064 ◽  
Author(s):  
S. A. Ahamed Ibrahim ◽  
P. Anbalagan ◽  
M. A. Jagabar Sathik

In this paper, a new asymmetric switched diode (ASD) multilevel inverter is presented for medium-voltage and high-power applications. The proposed converter consists of series connection basic unit with full-bridge inverter. In addition to this, a cascaded switched diode (CSD) structure is recommended to generate the higher number of voltage levels. Seven different algorithms are presented to determine the magnitudes of DC sources in CSD topology. To prove the advantages of proposed multilevel converter over recent multilevel converters in terms of blocking voltage, numbers of IGBTs and on-state switches are presented. To show the authority of the proposed multilevel inverter, it is simulated using MATLAB/Simulink and is experimentally tested using prototype model for 13-level inverter. Finally, various output voltage and current waveforms are shown to prove the dynamic behavior of proposed inverter.


2019 ◽  
Vol 28 (03) ◽  
pp. 1950038 ◽  
Author(s):  
Ebrahim Babaei ◽  
Concettina Buccella ◽  
Carlo Cecati

Multilevel inverters are generally used in medium-voltage and high-power applications. In this paper, a new 8-level basic structure for cascaded multilevel inverters is proposed. Based on proposed basic structure, two different cascaded multilevel topologies are proposed. The proposed cascaded multilevel inverters use less number of power switches, IGBTs and dc voltage sources compared with the conventional multilevel inverters. In order to generate all steps at the output voltage, three different algorithms to determine the amplitudes of dc voltage sources are presented. To reconfirm the performance and correct operation of the proposed topologies, the experimental results for a 15-level inverter are presented.


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