Minimal Output Impedance Required for Stability of Grid-Supporting Inverters

2021 ◽  
pp. 1-1
Author(s):  
Ron Ofir ◽  
Noa Zargari ◽  
Juri Belikov ◽  
Yoash Levron
Keyword(s):  
Output Impedance

A Study on Loop Gain Measurement Method Using Output Impedance in DC-DC Buck Converter

2018 ◽  
Vol E101.B (9) ◽  
pp. 1940-1948 ◽  
Author(s):  
Nobukazu TSUKIJI ◽  
Yasunori KOBORI ◽  
Haruo KOBAYASHI
Keyword(s):  
Measurement Method ◽  
Buck Converter ◽  
Loop Gain ◽  
Output Impedance ◽  
Gain Measurement

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals The Design of a Charge Pump Circuit and System with Input Impedance Modulation for a Flexible-Type Thermoelectric Generator with High-Output Impedance

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1212
Author(s):  
Kazuma Koketsu ◽  
Toru Tanzawa
Keyword(s):  
Input Impedance ◽  
Thermoelectric Generator ◽  
Charge Pump ◽  
Operating Voltage ◽  
Output Impedance ◽  
Two Phase ◽  
Pump System ◽  
High Output Impedance ◽  
A Charge ◽  
High Output

This paper describes a charge pump system for a flexible thermoelectric generator (TEG). Even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with low- and high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. How the system can be designed is also described in detail. A design demonstration was performed for the TEG with 400 Ω. The fabricated system was also measured with a flexible-type TEG based on carbon nanotubes. Even with an output impedance of 1.4 kΩ, the system converted thermal energy into electric power of 30 μW at 2.5 V to the following sensor ICs.

Design of LDO linear regulator with ultra low-output impedance buffer

2009 ◽  
Author(s):  
Jungsu Choi ◽  
Jungeui Park ◽  
Wooju Jeong ◽  
Junsang Lee ◽  
Seok Lee ◽  
...  
Keyword(s):  
Output Impedance ◽  
Linear Regulator

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

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