Full-Spectrum Spatial–Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits

2011 ◽  
Vol 19 (12) ◽  
pp. 2276-2289 ◽  
Author(s):  
Zyad Hassan ◽  
Nicholas Allec ◽  
Fan Yang ◽  
Li Shang ◽  
Robert P. Dick ◽  
...  
Author(s):  
Z. Hassan ◽  
N. Allec ◽  
Li Shang ◽  
R.P. Dick ◽  
V. Venkatraman ◽  
...  

Author(s):  
Xue-Xin Liu ◽  
Kuangya Zhai ◽  
Zao Liu ◽  
Kai He ◽  
Sheldon X.-D Tan ◽  
...  

2013 ◽  
Vol 562-565 ◽  
pp. 996-1000
Author(s):  
Zhen Zhou ◽  
Zheng Fang Dong ◽  
Li Shuang Feng ◽  
Kun Bo Wang ◽  
Yin Zhou Zhi

SOI Ridge nanowire waveguide (RNW) has advantages of strong confinement of optical mode, low propagation loss, small bend radius and fully compatible with CMOS technique, etc. An ultra-compact Y-branch coupler based on SOI RNW was designed and fabricated. Based on the finite-difference beam propagation method (FD-BPM), key parameters of the coupler were analyzed. Then the device was fabricated by electron beam lithography (EBL) and inductively coupled plasma (ICP) reactive ion etching. Results showed that the propagation loss of RNW was 1.89 dB/mm, and the radiation loss of the coupler with branch angle of 30° was only 0.66 dB. Compared with traditional Y-branch coupler, the proposed structure were more promising for high density optical integrated circuits.


Author(s):  
Edward Keyes ◽  
Jason Abt

Abstract Historically, the extraction of circuitry from an integrated circuit was normally within the abilities of the average FA laboratory and could be accomplished with little more than an optical microscope and film camera. Dramatic increases in the level of integration and number of metal interconnect levels coupled with shrinking feature sizes have rendered these techniques obsolete. This paper describes techniques and methods for the fast, semi-automated extraction of detailed circuit schematics from modern, nanometer scale integrated circuits.


2007 ◽  
Author(s):  
Samuel J. Dickerson ◽  
Arnaldo J. Noyola ◽  
Steven P. Levitan ◽  
Donald M. Chiarulli

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