Placement techniques for the physical synthesis of nanometer-scale integrated circuits

2009 ◽  
Author(s):  
Natarajan Viswanathan
Keyword(s):  
Integrated Circuits ◽  
Nanometer Scale ◽  
Physical Synthesis

Nanometer-Scale SOI Based Y-Branch Couplers for High Density Optical Integrated Circuits

2013 ◽  
Vol 562-565 ◽  
pp. 996-1000
Author(s):  
Zhen Zhou ◽  
Zheng Fang Dong ◽  
Li Shuang Feng ◽  
Kun Bo Wang ◽  
Yin Zhou Zhi
Keyword(s):  
Integrated Circuits ◽  
Inductively Coupled Plasma ◽  
Beam Propagation Method ◽  
High Density ◽  
Propagation Loss ◽  
Nanometer Scale ◽  
Optical Integrated Circuits ◽  
Inductively Coupled ◽  
Branch Angle ◽  
Strong Confinement

SOI Ridge nanowire waveguide (RNW) has advantages of strong confinement of optical mode, low propagation loss, small bend radius and fully compatible with CMOS technique, etc. An ultra-compact Y-branch coupler based on SOI RNW was designed and fabricated. Based on the finite-difference beam propagation method (FD-BPM), key parameters of the coupler were analyzed. Then the device was fabricated by electron beam lithography (EBL) and inductively coupled plasma (ICP) reactive ion etching. Results showed that the propagation loss of RNW was 1.89 dB/mm, and the radiation loss of the coupler with branch angle of 30° was only 0.66 dB. Compared with traditional Y-branch coupler, the proposed structure were more promising for high density optical integrated circuits.

An Advanced Integrated Circuit Analysis System

2006 ◽  
Author(s):  
Edward Keyes ◽  
Jason Abt
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Optical Microscope ◽  
Circuit Analysis ◽  
Nanometer Scale ◽  
Automated Extraction ◽  
Analysis System ◽  
Detailed Circuit

Abstract Historically, the extraction of circuitry from an integrated circuit was normally within the abilities of the average FA laboratory and could be accomplished with little more than an optical microscope and film camera. Dramatic increases in the level of integration and number of metal interconnect levels coupled with shrinking feature sizes have rendered these techniques obsolete. This paper describes techniques and methods for the fast, semi-automated extraction of detailed circuit schematics from modern, nanometer scale integrated circuits.

Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

2007 ◽  
Author(s):  
Samuel J. Dickerson ◽  
Arnaldo J. Noyola ◽  
Steven P. Levitan ◽  
Donald M. Chiarulli
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Nanometer Scale ◽  
Lab On Chip ◽  
On Chip

Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits

2009 ◽  
Vol 28 (6) ◽  
pp. 860-873 ◽  
Author(s):  
Z. Hassan ◽  
N. Allec ◽  
Li Shang ◽  
R.P. Dick ◽  
V. Venkatraman ◽  
...  
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Nanometer Scale

Auger and TEM analysis of multilayer IC contacts

1994 ◽  
Vol 52 ◽  
pp. 818-819
Author(s):  
R. W. Buttry ◽  
C. R. Hills ◽  
G. C. Nelson ◽  
T. Tribble
Keyword(s):  
Integrated Circuits ◽  
Ion Beam ◽  
Thin Layers ◽  
Nanometer Scale ◽  
Ion Beam Sputtering ◽  
Tem Analysis ◽  
Transmission Electron ◽  
Layer Structures ◽  
Beam Sputtering ◽  
Depth Scale

With the continued shrinkage of the dimensions (both laterally and in depth) of integrated circuits (IC), knowledge of the interactions that occur over nanometer scale distances becomes increasingly important. This requirement has pushed the capabilities of the tools used to analyze these structuresto their maximum. Two techniques which are frequently used to analyze thin layer structures are AugerElectron Spectroscopy (AES) and Transmission Electron Microscopy (TEM).AES combined with ion beam sputtering is used to measure the elemental composition as a function of sputter time. With suitable calibration, the sputter time scale can be converted to a depth scale. Theprofiles can also be used to study the interfacial reactions for thin layers. TEM is frequently used to accurately measure layer thicknesses and the layer elemental constituents can be identified byEnergy Dispersive Spectroscopy (EDS). When the layer thicknesses approach a few tens of A there are problems associated with interpreting the data from both of these techniques, particularly the data obtained near the interfaces.

Full-Spectrum Spatial–Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits

2011 ◽  
Vol 19 (12) ◽  
pp. 2276-2289 ◽  
Author(s):  
Zyad Hassan ◽  
Nicholas Allec ◽  
Fan Yang ◽  
Li Shang ◽  
Robert P. Dick ◽  
...  
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Nanometer Scale ◽  
Temporal Dynamic ◽  
Full Spectrum

Scanning Kelvin Force and Capacitance Microscopy Applications

1998 ◽  
Vol 4 (S2) ◽  
pp. 330-331
Author(s):  
R.J. Kline ◽  
J.F. Richards ◽  
P.E. Russell
Keyword(s):  
Integrated Circuits ◽  
Scanning Probe Microscopy ◽  
Scanning Probe ◽  
Nanometer Scale ◽  
Kelvin Probe ◽  
Probe Microscopy ◽  
Kelvin Probe Microscopy ◽  
Small Capacitance ◽  
Force Monitoring ◽  
Work Functions

Scanning Probe Microscopy (SPM) is being developed as a possible solution to the problems inherent with analyzing the nanometer scale electronic properties of ULSI integrated circuits. Scanning Kelvin Probe Microscopy (SKPM) and Scanning Capacitance Microscopy (SCM) are both being developed to provide two dimensional dopant profiles of semiconductor devices. SKPM can also determine surface potentials, work functions, dielectric properties, and capacitance.SKPM is based on the concept of Kelvin probe oscillating capacitor work function measurements. The small capacitance area of the SKPM tip and the high resistance of the system produce difficulties in monitoring and minimizing the current in the system. SKPM solves this problem by utilizing the force monitoring capability of the SPM to minimize the Kelvin force instead of the current. An AC voltage applied to the cantilever produces a DC force and AC forces at the AC frequency and the first harmonic of the AC frequency.

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