DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

2020 ◽  
Vol 28 (4) ◽  
pp. 1030-1042 ◽  
Author(s):  
Dave Y.-W. Lin ◽  
Charles H.-P. Wen
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Rate Reduction ◽  
Flip Flop ◽  
Soft Error Rate

Output remapping technique for critical paths soft-error rate reduction

2010 ◽  
Vol 4 (4) ◽  
pp. 325-333 ◽  
Author(s):  
Q. Ding ◽  
H. Yang ◽  
Y. Wang ◽  
H. Wang ◽  
R. Luo
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Critical Paths

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

2009 ◽  
Vol 25 (2-3) ◽  
pp. 197-207 ◽  
Author(s):  
Mihir R. Choudhury ◽  
Quming Zhou ◽  
Kartik Mohanram
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Circuit Optimization ◽  
Rate Reduction ◽  
Soft Error Rate ◽  
Filter Insertion

Soft Error Rate Reduction in Dynamic Memory with Trench Capacitor Cell

1986 ◽  
Author(s):  
H. Ishiuchi ◽  
T. Watanabe ◽  
T. Tanaka ◽  
K. Kishi ◽  
M. Ishikawa ◽  
...  
Keyword(s):  
Error Rate ◽  
Soft Error ◽  
Rate Reduction ◽  
Dynamic Memory ◽  
Soft Error Rate ◽  
Capacitor Cell
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