ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Credits

Listings of the ISTFA 1998 Organizing, Steering, Abstract Review, and Workshop Committees and other contributors.

Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate

Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.

The Effect of Ball Pad Metallurgy and Ball Composition on Solder Ball Integrity of Plastic Ball Grid Array Packages

Ball shear forces of plastic ball grid array (PBGA) packages are found to decrease after reliability test. Packages with different ball pad metallurgy form different intermetallic compounds (IMC) thus ball shear forces and failure modes are different. The characteristic and dynamic process of IMC formed are decided by ball pad metallurgy which includes Ni barrier layer and Au layer thickness. Solder ball composition also affects IMC formation dynamic process. There is basically no difference in ball shear force and failure mode for packages with different under ball pad metallurgy before reliability test. However shear force decreased and failure mode changed after reliability test, especially when packages exposed to high temperature. Major difference in ball shear force and failure mode was found for ball pad metallurgy of Ni barrier layer including Ni-P, pure Ni and Ni-Co. Solder ball composition was found to affect the IMC formation rate.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Layout Overlay Techniques to Improve Failure Analysis

New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

Application of EMS Analysis to Failure in Cell Area of Memory Device

EMS analysis is widely used in the failure analysis of the semiconductor. Moreover, the availability is widely evaluated. However, EMS analysis is not often used for the defect (1 Bit failure, Word Line failure, Bit Line failure, etc.) in the cell area in the memory device, because information on Fail Bit Map can be facilitated. Recently, make minutely advancing, and it is impossible to detect the defective cause only by Fail Bit Map information. We found the effectiveness as follows by the use of EMS analysis for a defective sample with Fail Bit Map information to solve such a problem. It leads to shortening analysis TAT because a defective part can be specified. Moreover, because the SHORT/OPEN mode can be divided, it is useful for the presumption of a defective mode. Furthermore, it is effective also to the confirmation of the presence of the redundancy and the confirmation of Fail Bit Map. Thus, because the application of EMS analysis for the defect in the cell area of the memory device is very effective to detect a defective cause, I want to recommend it by all means.

Making the Most of the Internet for Failure Analysis

The growth of the Internet over the past four years provides the failure analyst with a new media for communicating his results. The new digital media offers significant advantages over analog publication of results. Digital production, distribution and storage of failure analysis results reduces copying costs and paper storage, and enhances the ability to search through old analyses. When published digitally, results reach the customer within minutes of finishing the report. Furthermore, images on the computer screen can be of significantly higher quality than images reproduced on paper. The advantages of the digital medium come at a price, however. Research has shown that employees can become less productive when replacing their analog methodologies with digital methodologies. Today's feature-filled software encourages "futzing," one cause of the productivity reduction. In addition, the quality of the images and ability to search the text can be compromised if the software or the analyst does not understand this digital medium. This paper describes a system that offers complete digital production, distribution and storage of failure analysis reports on the Internet. By design, this system reduces the futzing factor, enhances the ability to search the reports, and optimizes images for display on computer monitors. Because photographic images are so important to failure analysis, some digital image optimization theory is reviewed.

Techniques to Remove the C4 Die from a Ceramic Package

C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.

Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.