scholarly journals A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

2019 ◽  
Vol 23 (1) ◽  
Author(s):  
Jihene Mallek ◽  
Houda Daoud ◽  
Rahma Aloulou ◽  
Hassene Mnif ◽  
Mourad Loulou
Keyword(s):  
Dynamic Range ◽  
Pole Placement ◽  
Mobile Wimax ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Placement Method ◽  
Channel Bandwidth ◽  
Sigma Delta Adc ◽  
Multi Mode ◽  
Channel Bandwidths

Objective: In this work the design of a fourth-order Reconfigurable Sigma Delta analog-to-digital converter (ΣΔ ADC) for 5MHz, 7MHz or 10MHz channel bandwidths are presented. Materials and methods: Our design technique aims to keep the same ADC architecture in response to multi-band and multi-mode aspects of Mobile WiMAX standard. To this end, we set each sampling frequency corresponding to each channel bandwidth, in order that the same OSR value would be kept for the different channel bandwidths. This technique is intended to optimize the power and area of the ADC that efficiently covers varying channel bandwidths. Moreover, we use the pole placement method to calculate the optimized filter coefficients of Continuous-Time Sigma-Delta (CT ΣΔ) ADC. Results and discussion: Over 5MHz, 7MHz and 10MHz channel bandwidths, the ADC achieved 72.89dB, 67.26dB and 66.47dB peak SNR values, respectively and a dynamic range of 73.5dB, 69.47dB and 66.5dB respectively with only 28mW, 28.2mW and 28.6mW power consumption respectively. Conclusions: The design of the proposed reconfigurable ADC intended for use in the mobile WiMAX standard were achieved. Moreover, the results obtained are satisfactory and are in accordance with theoretical expectations.

Adaptive Blocker Rejection Continuous-Time $\Sigma \Delta $ ADC for Mobile WiMAX Applications

2009 ◽  
Vol 44 (10) ◽  
pp. 2766-2779 ◽  
Author(s):  
Hyungseok Kim ◽  
Junghan Lee ◽  
Tino Copani ◽  
Seyfi Bazarjani ◽  
Sayfe Kiaei ◽  
...  
Keyword(s):  
Continuous Time ◽  
Mobile Wimax ◽  
Sigma Delta ◽  
Sigma Delta Adc

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

scholarly journals Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter

2016 ◽  
Vol 4 (3) ◽  
pp. 85-90
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
System Level ◽  
Dynamic Parameters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Matlab Simulink ◽  
Analog To Digital ◽  
System Level Modeling ◽  
Self Test ◽  
Sigma Delta Adc

System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

scholarly journals Odd/Even Order Sampling Soft-Core Architecture towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4567
Author(s):  
Mfana ◽  
Hasan ◽  
Ali
Keyword(s):  
Industrial Revolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Sampling Techniques ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Fourth Industrial Revolution ◽  
Even Order

Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

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