Direct-Write Fabrication of Microchannel in Epoxy Matrix

Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault

This paper describes the fabrication of microchannels by direct-write assembly and their integration into CMOS circuit technologies. A robotic apparatus was used to deposit a fugitive ink filament on glass and CMOS chip substrates. An epoxy and a nanocomposite matrix were both used to enclose the ink which was subsequently removed under heat and pressure in order to form a microchannel. Here, we demonstrate the fabrication of a microchannel by direct-write assembly on top of a CMOS chip for potential laboratory-on-chip applications such as bioparticle detection and manipulation.

Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault

Direct-write fabrication process (DWFP) is a robotic deposition technique used to produce planar or three-dimensional (3D) microscale structures. These structures consist of paste-like filaments which are extruded through a micronozzle and deposited on a substrate [1]. These filaments are encapsulated inside an epoxy resin and then melted and removed by applying a moderate temperature for the creation of microfluidic components (e.g., microchannels, reservoirs). Following our previous reports [2–3] on the fabrication of microchannels by DWFP and high precision CMOS capacitive sensors [4], we present in this paper a microfluidic packaging procedure to realize microchannel and fluidic connections on top of CMOS chip. The compatibility of this fluidic packaging procedure with conventional electrical packaging techniques (e.g. wire bonding) is an important advantage of DWFP for CMOS based Laboratory-On-Chip applications. The fabrication challenges are discussed in the experimental section.


2009 ◽  
Vol 3 (4) ◽  
pp. 212-219 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Vamsy P. Chodavarapu

2007 ◽  
Vol 134 (1) ◽  
pp. 27-36 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault

1993 ◽  
Vol 04 (04) ◽  
pp. 351-358 ◽  
Author(s):  
TORSTEN LEHMANN

In this paper, an analogue, cascadable, CMOS chip set for artificial neural networks is presented. The chip set (a synapse chip and a neuron chip) offer on-chip back-propagation learning in a fully parallel, layered, feedforward network of arbitrary size and topology. The learning scheme is implemented with no extra circuits at the synapse sites (compared to the system without the learning scheme) and extra circuits of a complexity only about the same as the neurons at the neuron sites. Also, no additional wiring is required by the learning scheme. Measurements on an experimental chip set are presented.


2015 ◽  
Vol 25 (03) ◽  
pp. 1640023 ◽  
Author(s):  
Hans G. Kerkhoff ◽  
Hassan Ebrahimi

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50[Formula: see text]ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.


Author(s):  
K.K. Tokgoz ◽  
N. Fajri ◽  
Y. Seo ◽  
S. Kawai ◽  
K. Okada ◽  
...  

2009 ◽  
Vol 86 (10) ◽  
pp. 2104-2109 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault ◽  
Sumitra Rajagopalan ◽  
Vamsy P. Chodavarapu

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