Electro-Fluidic Packaging for CMOS Based Laboratory-on-Chips

2006 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault
Keyword(s):  
Epoxy Resin ◽  
High Precision ◽  
Three Dimensional ◽  
Fabrication Process ◽  
Moderate Temperature ◽  
Direct Write ◽  
Deposition Technique ◽  
Experimental Section ◽  
Cmos Chip ◽  
On Chip

Direct-write fabrication process (DWFP) is a robotic deposition technique used to produce planar or three-dimensional (3D) microscale structures. These structures consist of paste-like filaments which are extruded through a micronozzle and deposited on a substrate [1]. These filaments are encapsulated inside an epoxy resin and then melted and removed by applying a moderate temperature for the creation of microfluidic components (e.g., microchannels, reservoirs). Following our previous reports [2–3] on the fabrication of microchannels by DWFP and high precision CMOS capacitive sensors [4], we present in this paper a microfluidic packaging procedure to realize microchannel and fluidic connections on top of CMOS chip. The compatibility of this fluidic packaging procedure with conventional electrical packaging techniques (e.g. wire bonding) is an important advantage of DWFP for CMOS based Laboratory-On-Chip applications. The fabrication challenges are discussed in the experimental section.

A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications

2007 ◽  
Vol 4 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Qing Liu ◽  
Patrick Fay ◽  
Gary H. Bernstein
Keyword(s):  
Integrated Circuits ◽  
Coplanar Waveguide ◽  
Impedance Matching ◽  
Three Dimensional ◽  
Fabrication Process ◽  
Silicon Substrates ◽  
Electromagnetic Simulations ◽  
Communication Paradigm ◽  
On Chip ◽  
Test Chips

Quilt Packaging (QP), a novel chip-to-chip communication paradigm for system-in-package integration, is presented. By forming protruding metal nodules along the edges of the chips and interconnecting integrated circuits (ICs) through them, QP offers an approach to ameliorate the I/O speed bottleneck. A fabrication process that includes deep reactive ion etching, electroplating, and chemical-mechanical polishing is demonstrated. As a low-temperature process, it can be easily integrated into a standard IC fabrication process. Three-dimensional electromagnetic simulations of coplanar waveguide QP structures have been performed, and geometries intended to improve impedance matching at the interface between the on-chip interconnects and the chip-to-chip nodule structures were evaluated. Test chips with 100 μm wide nodules were fabricated on silicon substrates, and s-parameters of chip-to-chip interconnects were measured. The insertion loss of the chip-to-chip interconnects was as low as 0.2 dB at 40 GHz. Simulations of 20 μm wide QP structures suggest that the bandwidth of the inter-chip nodules is expected to be above 200 GHz.

A direct-write microfluidic fabrication process for CMOS-based Lab-on-Chip applications

2009 ◽  
Vol 86 (10) ◽  
pp. 2104-2109 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault ◽  
Sumitra Rajagopalan ◽  
Vamsy P. Chodavarapu
Keyword(s):  
Fabrication Process ◽  
Direct Write ◽  
Lab On Chip ◽  
On Chip

Direct-Write Fabrication of Microchannel in Epoxy Matrix

2005 ◽  
Author(s):  
Ebrahim Ghafar-Zadeh ◽  
Mohamad Sawan ◽  
Daniel Therriault
Keyword(s):  
Epoxy Matrix ◽  
Direct Write ◽  
Cmos Circuit ◽  
Cmos Chip ◽  
On Chip ◽  
Nanocomposite Matrix

This paper describes the fabrication of microchannels by direct-write assembly and their integration into CMOS circuit technologies. A robotic apparatus was used to deposit a fugitive ink filament on glass and CMOS chip substrates. An epoxy and a nanocomposite matrix were both used to enclose the ink which was subsequently removed under heat and pressure in order to form a microchannel. Here, we demonstrate the fabrication of a microchannel by direct-write assembly on top of a CMOS chip for potential laboratory-on-chip applications such as bioparticle detection and manipulation.

Direct-write grayscale lithography

2019 ◽  
Vol 8 (3-4) ◽  
pp. 163-169 ◽  
Author(s):  
Anya Grushina
Keyword(s):  
High Precision ◽  
Three Dimensional ◽  
Direct Write ◽  
Market Demand ◽  
3D Structures ◽  
Industrial Manufacturing ◽  
Scanning Probes ◽  
The Future ◽  
Micro Optics ◽  
New Applications

Abstract Grayscale lithography is used to produce three-dimensional (3D) structures on micro- and nanoscale. During the last decade, micro-optics and other applications were actively pushing the market demand for such structures. Direct-write systems that use lasers and heated scanning probes can be used for high-precision grayscale micro- and nanolithography. They provide solutions for the most demanding applications in research and industrial manufacturing. At both the micro- and nanoscale, though, some challenges remain, mainly related to throughput. Ongoing R&D efforts and emerging new applications drive several companies to join forces in order to meet the market demands for grayscale lithography of today and in the future.

Direct Write Assembly of Three-dimensional PZT Woodpile Structure

2011 ◽  
Vol 26 (5) ◽  
pp. 495-498
Author(s):  
Kun-Peng CAI ◽  
Jing-Bo SUN ◽  
Bo LI ◽  
Ji ZHOU
Keyword(s):  
Three Dimensional ◽  
Direct Write ◽  
Woodpile Structure

scholarly journals Electromechanically reconfigurable optical nano-kirigami

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Shanshan Chen ◽  
Zhiguang Liu ◽  
Huifeng Du ◽  
Chengchun Tang ◽  
Chang-Yin Ji ◽  
...  
Keyword(s):  
Near Infrared ◽  
Large Range ◽  
Three Dimensional ◽  
High Contrast ◽  
Si Substrate ◽  
High Modulation ◽  
Gold Nanostructure ◽  
Infrared Wavelengths ◽  
On Chip ◽  
Nano Electromechanical System

AbstractKirigami, with facile and automated fashion of three-dimensional (3D) transformations, offers an unconventional approach for realizing cutting-edge optical nano-electromechanical systems. Here, we demonstrate an on-chip and electromechanically reconfigurable nano-kirigami with optical functionalities. The nano-electromechanical system is built on an Au/SiO2/Si substrate and operated via attractive electrostatic forces between the top gold nanostructure and bottom silicon substrate. Large-range nano-kirigami like 3D deformations are clearly observed and reversibly engineered, with scalable pitch size down to 0.975 μm. Broadband nonresonant and narrowband resonant optical reconfigurations are achieved at visible and near-infrared wavelengths, respectively, with a high modulation contrast up to 494%. On-chip modulation of optical helicity is further demonstrated in submicron nano-kirigami at near-infrared wavelengths. Such small-size and high-contrast reconfigurable optical nano-kirigami provides advanced methodologies and platforms for versatile on-chip manipulation of light at nanoscale.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

2021 ◽  
Author(s):  
Khadidja Gaffour ◽  
Mohammed Kamel Benhaoua ◽  
Abou El Hassan Benyamina ◽  
Amit Kumar Singh
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Dimensional Network ◽  
On Chip
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