Multidisciplinary Placement Optimization of Heat Generating Electronic Components on Printed Circuit Boards Using Artificial Neural Networks

Author(s):  
Tohru Suwa ◽  
Hamid A. Hadim

A multidisciplinary placement optimization methodology for heat generating electronic components on printed circuit boards (PCBs) is presented. The methodology includes thermal, electrical and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location which are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology which is based on a combination of a superposition method and artificial neural networks (ANNs) is developed for this study. Two genetic algorithms with different thermal prediction methods are used in a cascade in the optimization process. The first genetic algorithm is based on simplified thermal network modeling and it is mainly aimed at finding component locations that avoid any overlap. Compact thermal models are used in the second genetic algorithm leading to more accurate thermal prediction which improves the placement optimization obtained using the first algorithm. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate the capabilities of the present methodology, a test case involving component placement on a PCB is presented.


2006 ◽  
Vol 129 (1) ◽  
pp. 90-97 ◽  
Author(s):  
Tohru Suwa ◽  
Hamid Hadim

A multidisciplinary placement optimization methodology for heat generating electronic components on printed circuit boards (PCBs) is presented. The methodology includes thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location which are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology which is based on a combination of a superposition method and artificial neural networks is developed for this study. Two genetic algorithms with different thermal prediction modules are used in a cascade in the optimization process. The first genetic algorithm uses simplified thermal network modeling and it is mainly aimed at finding component locations that avoid any overlap. Compact thermal models are used in the second genetic algorithm leading to more accurate thermal prediction which improves the placement optimization obtained using the first algorithm. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate its capabilities, the present methodology is applied to a test case involving placement optimization of several heat generating electronics components on a PCB.



Author(s):  
Tohru Suwa ◽  
Hamid Hadim

A multidisciplinary placement optimization methodology for heat generating electronic components on printed circuit boards (PCBs) in channel flow forced convection is presented. In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed. The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods. Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat flux at an arbitrary location on the board, while temperature rise due to multiple heat flux is calculated using a superposition method. Compact thermal models are used for the electronic components thermal modeling. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. For thermal model validation, the present thermal methodology predicts junction temperatures with maximum error of 1.8°C comparing to the conjugate solid/ fluid heat transfer analysis result. The present thermal modeling takes 12 seconds, while the conjugate analysis takes 30 hours for the validation on the same computer. To demonstrate the capabilities of the present methodology, a test case of component placement on a PCB is presented.



Author(s):  
Alexander Otto ◽  
Eberhard Kaulfersch ◽  
Prashant Kumar Singh ◽  
Claudio Romano ◽  
Marcus Hildebrandt ◽  
...  

Abstract Canary structures being used as early warning indicators represent an important tool for condition and health monitoring of electronic components and systems. In this paper, printed circuit boards with canary structures based on SMD 2512 ceramic chip resistors with reduced solder pad sizes were studied. Focus of these investigations was set on thermo-mechanical and mechanical stresses caused by passive thermal cycling as well as by vibrational loads. For this purpose, experimental methods such as deformation analysis and accelerated ageing tests as well as finite element based methods were applied. In addition, an outlook on the implementation of these canary structures into dual inverter electronic control boards for electrical powertrain applications will be given.



Author(s):  
А.В. Милов

В статье представлены математические модели на основе искусственных нейронных сетей, используемые для управления индукционной пайкой. Обучение искусственных нейронных сетей производилось с использованием многокритериального генетического алгоритма FFGA. This article presents mathematical models based on artificial neural networks used to control induction soldering. The artificial neural networks were trained using the FFGA multicriteria genetic algorithm. The developed models allow to control induction soldering under conditions of incomplete or unreliable information, as well as under conditions of complete absence of information about the technological process.



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