Sol-Gel Coating Facilitating Si-to-Si Wafer Bonding at Low Temperature

Silicon-to-silicon wafer bonding by sol-gel intermediate layer has been performed using acid-catalyzed tetraethylthosilicate-ethanol-water sol solution. High bond strength near to the fracture strength of bulk silicon is obtained at low temperature, for example 100°C. However, The bond efficiency and bond strength of this intermediate layer bonding sharply decrease when the bonding temperature increases to elevated temperature, such as 300 °C. The degradation of bond quality is found to be related to the decomposition of residual organic species at elevated bonding temperature. The bubble generation and the mechanism of the high bond strength at low temperature are exploited.

Development of Advanced Lead-Free Solder Based Interconnect Materials Containing Nanosized Y2O3 Particulates

This study addresses the development of lead-free nanocomposite solders. Lead-free composite solders were successfully synthesized, with varying amount of nanosized Y2O3 particulates incorporated into 95.8 Sn - 3.5 Ag - 0.7 Cu solder. These composite materials were fabricated using the powder metallurgy technique involving blending, compaction, sintering and extrusion. The extruded materials were then characterized in terms of their physical properties, microstructural development, thermal and mechanical properties. Results revealed that with the incorporation of increasing amount of reinforcements, the density values of the composite solders decreased while their corresponding porosity levels increased. Thermomechanical analysis of the solder nanocomposites showed that the use of reinforcements lowered the average coefficient of thermal expansion of the solder materials. Moreover, the results of mechanical property characterizations revealed that the addition of reinforcements aids in improving the overall strength of the nanocomposite solder. Particular emphasis is placed in this study to correlate the effect of increasing presence of Y2O3 particulates with the properties of the resultant nanocomposite materials. These advanced interconnect materials will benefit industries like the microelectronics flip chip assembly and packaging, MEMS systems and NEMS systems.

Effects of Dwell-Time and Ramp-Rate on The Thermal-Fatigue Life of SnAgCu Joints

Finite element analysis examines lead-free part-on-board accelerated thermal environments comprised of ramp and dwell times lasting between 5 and 15 minutes. The accumulated creep strain energy density is determined for each environment and used to evaluate cost-effective accelerated test environments.

Effects of Catalysts Supporting Layer on Carbon Nanotubes Growth

Due to their extraordinary electrical, thermal and mechanical properties, carbon nanotubes have been foreseen as potential materials for electronics devices in the future. To integrate carbon nanotubes in electronic applications, carbon nanotubes would need to be grown on different metal layer. In this study, carbon nanotubes growth with Ni as catalyst on three different support layers, Cu, Al and Cr, by hot filament chemical vapor deposition (HFCVD) is reported. The nanotubes were grown using C2H2 acetylene as carbon feedstock, in a hydrogen and nitrogen atmosphere. The catalyst layers and their support layers were deposited by magnetron sputtering technique. Deposited films were annealed at 600 °C for 10 minutes before exposing to C2H2 for the growth of nanotubes at same temperature for another 10 minutes. The effects of the support layer have been investigated with reference to nanotubes formation. The morphology and microstructure of the films were measured and analyzed by scanning electron microscopy (SEM) and Raman spectrometer. It was found that reaction of the catalyst with its supporting layer has significant effects on the growth of nanotubes. For Cu or Cr as support layer, its effect on the nanotubes growth was minimal. However Al support layer prevented the growth of carbon nanotubes. The possible mechanisms for the observed results are proposed.

Cooling System for a Portable Bio-Industry Centrifuge

A centrifuge is used in bio-industry to separate species in blood and other chemicals. Bio-industry requires a temperature of zero degree centigrade in the rotor compartment of a centrifuge where samples are placed. In general, the current portable centrifuge systems generate a temperature of about 22 °C in the rotor compartment when operating at 3000 RPM. The motor and the electronics are the primary sources of the heat generation in such centrifuge. The aim of this study is to develop an appropriate cooling system for a specific portable centrifuge used in separating bioparticles that generates a total heat of approximately 43 W. Experimental, analytical and computer simulation were employed to achieve the project objective of reducing and maintaining the rotor compartment temperature at zero degree C. The CFD code Simulation model predicted rotor compartment temperatures that were in good agreement with those of the experimental measurements within 3%. Having confidence in the CFD model, simulation was carried out to incorporate four TEC units that are embedded on the surface of the rotor compartment resulting in reduced temperature to zero degree C.

Reliability of Underfilled Chip Scale Packages Attached With Heat Sink

Chip Scale Packages (CSP) are ideal intermediates between Direct Chip Attach (DCA) and Ball Grid Array (BGA) technologies in terms of both size and cost. Depending upon the application, chip scale packages are either underfilled for better solder joint reliability or are attached with a heat sink to keep the operating temperature of the chip under control. In many applications, as discussed in this paper, both an underfill and a heat sink are required. Quite expectedly the addition of two more materials, heat sink and adhesive, in the board level assembly results in fresh reliability concerns. In particular, the requirements on the underfill material and the heat sink attach adhesive are more rigorous and needless to say, a proper understanding of process and material issues is needed to make such a choice. The inelastic strains experienced by the solder joint (related to the underfill) and the peeling stresses at the heat sink attach adhesive interfaces (related to the thermal adhesive) are used as metric for comparing the number of material choices that are available. Based on the results, it is shown that it is important to choose materials that are thermo-mechanically matched with the rest of the system.

Heat Conduction in Three Dimensional Stacked Packages

This paper presents the results of an analytical study of steady state heat conduction in multiple rectangular domains. Any finite number of such domains may be considered in the current study. The thermal conductivity and thickness of these domains may be different. The entire geometry composed of these connected domains is considered as adiabatic on the lateral surfaces and can be subjected to uniform convective cooling at one end. The other end of the geometry may be adiabatic and a specified, spatially varying heat generation rate can be applied in each of the domains. The solutions are found to be in agreement with known solutions for simpler geometries. The analytical solution presented here is very general in that it takes into account the interface resistances between the layers. One application of this analytical study relates to the thermal management of a 3-D stack of devices and interconnect layers. Another possible application is to the study of hotspots in a chip stack with non uniform heat generation. Many other potential applications may also be simulated.

Automated Assembly and Hermetic Packaging of MOEMS for Applications Requiring Extended Shelf-Lives

In this paper we describe two modular automated microassembly systems, along with a several packaging processes that have been integrated to produce reliable and cost-effective MOEMS devices. The automated and packaging systems consists of robotics such as pick and place, insertion and fastening, machine vision and controls, and processes such as die attach, solder reflow by laser, wire bonding and seam sealing. The target MOEMS devices are intended for applications requiring a minimum twenty year shelf-life.

High Reliability Flip Chip Using Low CTE Laminate Substrates

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Nano-Imprint Patterning of Nanowire Structures for Interconnect Study

A thermal nano-imprint method has been developed to pattern sub-40 nm polymer lines of Hydrogensilsesquioxane (HSQ) and electron beam resist ZEP 520A. The imprint template was the cross section surface of a selectively etched GaAs/AlGaAs heterostructure wafer. Silicon nanowires were formed using reactive ion etching (RIE) of a silicon-on-insulator wafer with the polymer nanolines as an etching mask. The obtained Si nanowires were well defined and continuous for a length up to hundreds of microns. Reaction of the silicon lines with a metal can lead to the formation of silicide interconnect lines, which is used to investigate the size effects on the transport and electromigration properties of interconnects for future microelectronics.