Modeling of optical alignment and metrology schemes used in integrated circuit manufacturing

1990 ◽  
Author(s):  
Chi-Min Yuan ◽  
Andrzej J. Strojwas
Keyword(s):  
Integrated Circuit ◽  
Integrated Circuit Manufacturing ◽  
Optical Alignment

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

scholarly journals Vision based wafer states detection in front opening unified pod load-port system

2021 ◽  
Vol 336 ◽  
pp. 02029
Author(s):  
Qiang Zhang ◽  
Xueying Sun ◽  
Mingmin Liu
Keyword(s):  
Integrated Circuit ◽  
Manufacturing Processes ◽  
Detection Accuracy ◽  
Traditional Methods ◽  
Integrated Circuit Manufacturing ◽  
Detection Approach ◽  
Port System

In modern integrated circuit manufacturing processes, wafers are always transported from one procedure to another. To reduce the risk of dust, Front Opening Unified Pod (FOUP) load-port system is always adopted. Misplaced wafers should be detected before transported. Traditional methods always fail to detect wafer states correctly. To improve detection accuracy, this paper proposed a vision based method. Wafer overlap and malposition detection approach based on modified YOLO-V3 algorithm was suggested. Experiment results shows superiority of the proposed approach.

Study on the formation and mechanism of aluminum bulge defect in semiconductor integrated circuit manufacturing

2021 ◽  
pp. 111661
Author(s):  
Liantao Ji ◽  
Chuanyong Jian ◽  
Qingcui Ma ◽  
Qingqing Liu ◽  
Yazhou Hua
Keyword(s):  
Integrated Circuit ◽  
Integrated Circuit Manufacturing
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