Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices

As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices.

Vision based wafer states detection in front opening unified pod load-port system

In modern integrated circuit manufacturing processes, wafers are always transported from one procedure to another. To reduce the risk of dust, Front Opening Unified Pod (FOUP) load-port system is always adopted. Misplaced wafers should be detected before transported. Traditional methods always fail to detect wafer states correctly. To improve detection accuracy, this paper proposed a vision based method. Wafer overlap and malposition detection approach based on modified YOLO-V3 algorithm was suggested. Experiment results shows superiority of the proposed approach.

Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

A Novel Framework of Lightweight Optimization Design of a Prototype Wafer Stage With Control Verification

Performance requirements of a higher throughput and accuracy in precision motion systems, such as wafer stage used in integrated circuit manufacturing, are ever increasing. The lightweight design, as one of the design methods, can results in less power consumption and less negative environmental impacts for the required high levels of acceleration. The aim of this research is to investigate the advantage of the lightweight design and to mitigate the negative effect caused by the flexible characteristics using an appropriate control method. In this paper, a prototype wafer stage is the analysis object. Since the mass of the horizontal drive motors accounts for a large proportion of the total mass of the wafer stage, a novel lightweight optimization frame based on the minimum motor mass is presented, while a Lorenz motor model based on finite element method (FEM) and artificial neural network (ANN) is firstly constructed. Then the controller adopting the PID with the maximum control bandwidth and pole placement method are designed. Through numerical analysis, the mass of the mover of the mover of this stage is reduced from 10.28 Kg to 6.078 Kg after lightweight optimization. Taking the Moving Average (MA) and Moving Standard Deviation (MSD) of the servo error in Z-direction as the control index, a closed-loop simulation result shows that the lightweight wafer stage can separately fulfil the requirement of the MA and MSD of the servo error in z-direction within 20nm and 30nm just as the current rigid-body wafer stage without the lightweight optimization.