A scalable nanoimprint lithography process to manufacture diffractive optics and metalenses with high aspect ratio nanofeatures using high refractive index nanocrystals

Author(s):  
Vincent Einck ◽  
Jim Watkins ◽  
Amir Arbabi ◽  
Andrew McClung ◽  
Mahsa Torfeh ◽  
...  
ACS Photonics ◽  
2021 ◽  
Author(s):  
Vincent J. Einck ◽  
Mahsa Torfeh ◽  
Andrew McClung ◽  
Dae Eon Jung ◽  
Mahdad Mansouree ◽  
...  

2012 ◽  
Vol 23 (50) ◽  
pp. 505502 ◽  
Author(s):  
Etsuo Maeda ◽  
Yaerim Lee ◽  
Youjiro Kobayashi ◽  
Akiko Taino ◽  
Mari Koizumi ◽  
...  

2013 ◽  
Vol 104 ◽  
pp. 58-63 ◽  
Author(s):  
Rizwan Muhammad ◽  
Si-Hyeong Cho ◽  
Jung-Hwan Lee ◽  
Jin-Goo Park

2008 ◽  
Vol 2008 ◽  
pp. 1-4 ◽  
Author(s):  
K. O. Aung ◽  
C. Shankaran ◽  
R. Sbiaa ◽  
E. L. Tan ◽  
S. K. Wong ◽  
...  

Discrete track media (DTM) fabricated by nanoimprint lithography (NIL) is considered as a potential technology for future hard disk drives (HDD). In the fabrication of a master mold for NIL, patterning the resist tracks with a narrow distribution in the width is the first critical step. This paper reports the challenges involved in the fabrication of high aspect ratio discrete tracks on Polymethylmethacrylate (PMMA) resist by means of electron beam lithography. It was observed that fabrication parameters applied for successful patterning of discrete tracks in nanoscale length were not directly suitable for the patterning of discrete tracks in micron scale. Hence different approaches such as thick layer resist coating, introducing of post exposure baking process, and varying of exposure parameters were used in order to achieve uniform sharp discrete tracks in micron scale length on the resist. The optimal parameters were used to pattern 20 μm long tracks with 70 nm track pitch on the resist.


2001 ◽  
Author(s):  
Gary O’Brien ◽  
Xing Cheng ◽  
L. J. Guo

Abstract Sub-micron width high aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool equipped with a time multiplexed plasma etch/passivation cycle scheme. The oxide mask is patterned by nanoimprint lithography and minimizes lateral trench etching by adjusting the significant etch parameters. High aspect ratio trench arrays 350nm wide with a 700nm period are etched to a depth of 10 μm with typical sidewall asperities on the order of 30nm. A dual etch process is used to reduce scalloping near the trench surface using HBr/Cl to etch the initial 500nm followed by the STS process using C4F8/SF6 chemistry. The dual etch process resulted in a reduction of sidewall asperities from 75nm to less than 25nm. In addition, the dual etch process reduced the trench array depth variation from a measured standard deviation of 0.7 to 0.1 representing significant improvement of etch repeatability across the wafer sample.


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