Small-signal optimization approach to design of microwave signal switch ICs on MOS transistors

2017 ◽  
Vol 46 (5) ◽  
pp. 365-369 ◽  
Author(s):  
V. V. Elesin ◽  
G. N. Nazarova ◽  
N. A. Usachev ◽  
G. V. Chukov
Author(s):  
A. Bracale ◽  
N. Fel ◽  
V. Ferlet-Cavrois ◽  
D. Pasquet ◽  
J.L. Gautier ◽  
...  

2002 ◽  
Vol 49 (5) ◽  
pp. 871-880 ◽  
Author(s):  
P. Sakalas ◽  
H.G. Zirath ◽  
A. Litwin ◽  
M. Schroter ◽  
A. Matulionis

Author(s):  
Du Lin ◽  
Yang Xiaofeng ◽  
Li Yang ◽  
Zhang Jincheng ◽  
Hao Yue
Keyword(s):  

2015 ◽  
Vol 15 (3) ◽  
pp. 139-151 ◽  
Author(s):  
R. Sotner ◽  
J. Jerabek ◽  
N. Herencsar ◽  
K. Vrba ◽  
A. Lahiri ◽  
...  

AbstractThe paper deals with precise analysis of simple AC variable gain CMOS amplifier. The circuit can be used as a simple voltage follower (6 MOS transistors are required) or amplifier. The main attention of this work is focused on a small-signal model of the proposed block and effects of additional passive network leading to compensation of its instability. The continuous gain adjusting in range from 1.1 to 10 (0.8 – 20 dB and with bandwidth 4.9 - 90 MHz at 5 pF load capacitance) is possible and the proposed amplifier is suitable for implementation in systems, where lower range of gain adjusting and large dynamical range is required. Theoretical analyses are supported by PSpice simulations (TSMC 0.18 um technological models) and experimental measurements with commercially available CMOS transistor fields (ALD1106/7) also confirm the discussed behavior of the amplifier.


Author(s):  
A. Bracale ◽  
D. Pasquet ◽  
J.L. Gautier ◽  
V. Ferlet ◽  
N. Fel ◽  
...  

1991 ◽  
Vol 01 (02) ◽  
pp. 205-228 ◽  
Author(s):  
FATHI M.A. SALAM ◽  
MYUNG-RYUL CHOI

All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 μm CMOS n-well process via MOSIS.


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