A 2.4 GHz 87 μW low-noise amplifier in 65 nm CMOS for IoT applications

2021 ◽  
pp. 2150485
Author(s):  
Jingwei Wu ◽  
Benqing Guo ◽  
Huifen Wang ◽  
Haifeng Liu ◽  
Lei Li ◽  
...  
Keyword(s):  
Low Power ◽  
Performance Metrics ◽  
Power Saving ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Battery Life ◽  
Current Reuse ◽  
Transconductance Amplifier ◽  
Noise Amplifier ◽  
Boosting Technique

As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, [Formula: see text]-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based [Formula: see text]-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a [Formula: see text] power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 [Formula: see text]W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

A low power low noise amplifier employing negative feedback and current reuse techniques

2016 ◽  
Vol 49 ◽  
pp. 49-56 ◽  
Author(s):  
Roya Jafarnejad ◽  
Abumoslem Jannesari ◽  
Abdolreza Nabavi ◽  
Ali Sahafi
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Reuse ◽  
Noise Amplifier

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

Tunable Low-Power Low-Noise Amplifier for Healthcare Applications

2021 ◽  
Author(s):  
Rafael Vieira ◽  
Nuno Horta ◽  
Nuno Lourenço ◽  
Ricardo Póvoa
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Healthcare Applications ◽  
Noise Amplifier

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems

Integration ◽  
2019 ◽  
Vol 69 ◽  
pp. 189-197 ◽  
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Low Power ◽  
Wireless Systems ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier
Sign in / Sign up

Export Citation Format

Share Document