HIGH-SPEED PARALLEL VLSI ARCHITECTURES FOR IMAGE DECORRELATION

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/ decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compression schemes and their difficulties.

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PMAC: A POLYGON MATCHING CHIP

International Journal of Pattern Recognition and Artificial Intelligence ◽

10.1142/s0218001495000171 ◽

1995 ◽

Vol 09 (02) ◽

pp. 367-385 ◽

Cited By ~ 1

Author(s):

RAGHU SASTRY ◽

N. RANGANATHAN

Keyword(s):

High Speed ◽

Robot Vision ◽

Edge Length ◽

Affine Transformations ◽

Vlsi Architectures ◽

Vlsi Chip ◽

Vlsi Technology ◽

Computationally Intensive ◽

Local Shape Descriptors ◽

Cmos Vlsi

The recognition of polygons in 3-D space is an important task in robot vision. Advances in VLSI technology have now made it possible to implement inexpensive, efficient and very fast custom designs. The authors have earlier proposed a class of VLSI architectures for this computationally intensive task, which makes use of a set of local shape descriptors for polygons which are invariant under affine transformations, i.e. translation, scaling, rotation and orthographic projection from 3-D to any 2-D plane. This paper discusses the design and implementation of PMAC, a prototype for polygon matching, as a custom CMOS VLSI chip. The recognition procedure is based on the matching of edge-length ratios using a simplified version of the dynamic programming procedure commonly employed for string matching. The matching procedure also copes with partial occlusions of polygons. The implemented architecture is systolic and fully utilizes the principles of pipelining and parallelism in order to obtain high speed and throughput.

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Very high speed real-time IIR digital filter structures: suitable for VLSI implementation

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.393798 ◽

2002 ◽

Author(s):

K.K. Dhar

Keyword(s):

Real Time ◽

Digital Filter ◽

High Speed ◽

Vlsi Implementation ◽

Filter Structures ◽

Very High

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Lossless Image Compression Techniques: A State-of-the-Art Survey

Symmetry ◽

10.3390/sym11101274 ◽

2019 ◽

Vol 11 (10) ◽

pp. 1274 ◽

Cited By ~ 1

Author(s):

Md. Atiqur Rahman ◽

Mohamed Hamada

Keyword(s):

Image Compression ◽

High Speed ◽

Communication Theory ◽

State Of The Art ◽

Signal To Noise Ratio ◽

Daily Basis ◽

The State ◽

Huge Amount ◽

Lossless Image Compression ◽

Art Techniques

Modern daily life activities result in a huge amount of data, which creates a big challenge for storing and communicating them. As an example, hospitals produce a huge amount of data on a daily basis, which makes a big challenge to store it in a limited storage or to communicate them through the restricted bandwidth over the Internet. Therefore, there is an increasing demand for more research in data compression and communication theory to deal with such challenges. Such research responds to the requirements of data transmission at high speed over networks. In this paper, we focus on deep analysis of the most common techniques in image compression. We present a detailed analysis of run-length, entropy and dictionary based lossless image compression algorithms with a common numeric example for a clear comparison. Following that, the state-of-the-art techniques are discussed based on some bench-marked images. Finally, we use standard metrics such as average code length (ACL), compression ratio (CR), pick signal-to-noise ratio (PSNR), efficiency, encoding time (ET) and decoding time (DT) in order to measure the performance of the state-of-the-art techniques.

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A novel ortho normalized multi-stage discrete fast Stockwell transform based memory-aware high-speed VLSI implementation for image compression

Multimedia Tools and Applications ◽

10.1007/s11042-018-7055-5 ◽

2019 ◽

Vol 78 (13) ◽

pp. 17673-17699 ◽

Cited By ~ 1

Author(s):

G kiranmaye ◽

Srinivasulu Tadisetty

Keyword(s):

Image Compression ◽

High Speed ◽

Vlsi Implementation ◽

Multi Stage ◽

Stockwell Transform

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Implementation of the JPEG on DSP Processors

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.34-35.1536 ◽

2010 ◽

Vol 34-35 ◽

pp. 1536-1539 ◽

Cited By ~ 3

Author(s):

Shi Jun Li ◽

Xi Long Qu ◽

Qiang Li

Keyword(s):

Image Compression ◽

Real Time ◽

High Speed ◽

International Standards ◽

Surveillance Systems ◽

Operation Performance ◽

Real Time Processing ◽

Dct Transform ◽

Digital Image Compression ◽

Dsp Processors

this paper introduces the design and implementation of JPEG image compression based on the high speed DSP TMS320VC5416 available from Texas Instruments. Especially, the realization and optimization of DCT transform is discussed and the image Lena is compressed with different way. Experiments show that the reconstructed images have PSNR above 34dB . JPEG algorithm is a digital image compression algorithm with high compression ratio, little distortion characteristics, and has been identified as international standards. This standard has been widely used in digital cameras, surveillance systems, mobile phones, video phones, and many other aspects. It is important to research and realize a real-time image compress system Using JPEG. DSP is used in real-time processing and portable applications with special hardware structure. DSP with high processing speed and excellent operation performance is particularly adapted to image processing. This article introduces DSP-based implementation of JPEG[1].

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