Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality

2016 ◽  
Vol 25 (06) ◽  
pp. 1650062 ◽  
Author(s):  
Gang Chen ◽  
Kai Huang ◽  
Long Cheng ◽  
Biao Hu ◽  
Alois Knoll

Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.

2014 ◽  
Vol 13 (4s) ◽  
pp. 1-25 ◽  
Author(s):  
Jack Whitham ◽  
Neil C. Audsley ◽  
Robert I. Davis

2020 ◽  
Vol 34 (23) ◽  
pp. 2050242
Author(s):  
Yao Wang ◽  
Lijun Sun ◽  
Haibo Wang ◽  
Lavanya Gopalakrishnan ◽  
Ronald Eaton

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.


2020 ◽  
Vol 32 ◽  
pp. 03047
Author(s):  
Anushka Kulkarni ◽  
Prachi Kedar ◽  
Aishwarya Pupala ◽  
Priyanka Shingane

Currency is used to carry out not only business but also for various other transactions to get access to various services and commodities. There are a total of 7 denominations for the Indian currency each with unique features to distinguish them from each other and with various and distinct security features to prevent them from fraudulent copying. However,with the evolution of technology, there is also an increase in the ways in which fake forms of these currencies are created. These fake or counterfeit notes have various ill-effect on society. The proposed system will be used to check the genuine Indian currency notes and to find the denomination of the currency note. Comparative study for various image processing algorithms was conducted to identify and select the one which will be able to extract more prominent features,and is also better in terms of processing time,outlier rejection, efficiency in computation and in feature matching. After which a real time system is created for currency detection in real time.


2010 ◽  
Vol 46 (2) ◽  
pp. 251-300 ◽  
Author(s):  
Heiko Falk ◽  
Paul Lokuciejewski

Abstract The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the worst-case execution time (WCET) of a system during code generation and in systematically optimizing code to reduce WCET. This article presents concepts and infrastructures for WCET-aware code generation and optimization techniques for WCET reduction. All together, they help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real-time system by allowing to use tailored hardware.


2014 ◽  
Vol 577 ◽  
pp. 865-872
Author(s):  
Jun Yi Li ◽  
Yi Zhang ◽  
Ren Fa Li

The Real-time system estimates the worst-case execution time (WCET) of the program to ensure the real-time requirements of the system. In this paper, a test method based on Associative Process Communication (APC) is put forward. First it tests the WCET value of basic blocks of ICFG through the use of APC algorithm, and then estimates the WCET by analyzing the worst execution path of the basic block. APC test method tests all benchmarks of Mälardalen. And the test results show that the proposed test method is precise and effective, and the test error is within the theoretical analysis.


Author(s):  
Jia Xu

Methods for handling process underruns and overruns when scheduling a set of real-time processes increase both system utilization and robustness in the presence of inaccurate estimates of the worst-case computations of real-time processes. In this paper, we present a method that efficiently re-computes latest start times for real time processes during run-time in the event that a real-time process is preempted or has completed (or overrun). The method effectively identifies which process latest start times will be affected by the preemption or completion of a process. Hence the method is able to effectively reduce real-time system overhead by selectively re-computing latest start times for the specific processes whose latest start times are changed by a process preemption or completion, as opposed to indiscriminately re-computing latest start times for all the processes.


Author(s):  
Alan Grigg ◽  
Lin Guan

This chapter describes a real-time system performance analysis approach known as reservation-based analysis (RBA). The scalability of RBA is derived from an abstract (target-independent) representation of system software components, their timing and resource requirements and run-time scheduling policies. The RBA timing analysis framework provides an evolvable modeling solution that can be instigated in early stages of system design, long before the software and hardware components have been developed, and continually refined through successive stages of detailed design, implementation and testing. At each stage of refinement, the abstract model provides a set of best-case and worst-case timing ‘guarantees’ that will be delivered subject to a set of scheduling ‘obligations’ being met by the target system implementation. An abstract scheduling model, known as the rate-based execution model then provides an implementation reference model with which compliance will ensure that the imposed set of timing obligations will be met by the target system.


2012 ◽  
pp. 637-668
Author(s):  
Alan Grigg ◽  
Lin Guan

This chapter describes a real-time system performance analysis approach known as reservation-based analysis (RBA). The scalability of RBA is derived from an abstract (target-independent) representation of system software components, their timing and resource requirements and run-time scheduling policies. The RBA timing analysis framework provides an evolvable modeling solution that can be instigated in early stages of system design, long before the software and hardware components have been developed, and continually refined through successive stages of detailed design, implementation and testing. At each stage of refinement, the abstract model provides a set of best-case and worst-case timing ‘guarantees’ that will be delivered subject to a set of scheduling ‘obligations’ being met by the target system implementation. An abstract scheduling model, known as the rate-based execution model then provides an implementation reference model with which compliance will ensure that the imposed set of timing obligations will be met by the target system.


2015 ◽  
Vol 2 (1) ◽  
pp. 35-41
Author(s):  
Rivan Risdaryanto ◽  
Houtman P. Siregar ◽  
Dedy Loebis

The real-time system is now used on many fields, such as telecommunication, military, information system, evenmedical to get information quickly, on time and accurate. Needless to say, a real-time system will always considerthe performance time. In our application, we define the time target/deadline, so that the system should execute thewhole tasks under predefined deadline. However, if the system failed to finish the tasks, it will lead to fatal failure.In other words, if the system cannot be executed on time, it will affect the subsequent tasks. In this paper, wepropose a real-time system for sending data to find effectiveness and efficiency. Sending data process will beconstructed in MATLAB and sending data process has a time target as when data will send.


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