Noise Bus Modeling in Network on Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850149 ◽  
Author(s):  
Moez Balti
Keyword(s):  
Bit Error Rate ◽  
Network On Chip ◽  
Waveform Relaxation ◽  
Signal Source ◽  
Electrical Circuits ◽  
Coupling Noise ◽  
Current Voltage ◽  
Coupled Lines ◽  
Simulation Results ◽  
On Chip

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections. The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines. We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs.

Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

2016 ◽  
Vol 13 (10) ◽  
pp. 7592-7598
Author(s):  
J Kalaivani ◽  
B Vinayagasundaram
Keyword(s):  
Packet Loss ◽  
Probability Function ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Communication Architecture ◽  
Data Packets ◽  
Oblivious Routing ◽  
Simulation Results ◽  
On Chip ◽  
Load Balanced

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Network ◽  
Communication Performance ◽  
Simulation Results ◽  
On Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

IMPROVED MODIFIED FAT-TREE TOPOLOGY NETWORK-ON-CHIP

2011 ◽  
Vol 20 (04) ◽  
pp. 757-780 ◽  
Author(s):  
ABDELHAFID BOUHRAOUA ◽  
MUHAMMAD E. S. ELRABAA
Keyword(s):  
Network Performance ◽  
Network On Chip ◽  
Tree Topology ◽  
Traffic Model ◽  
Bursty Traffic ◽  
Traffic Models ◽  
Mesh Topology ◽  
Simulation Results ◽  
On Chip ◽  
Place And Route

C-based cycle-accurate simulations are used to evaluate the performance of a Network-on-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformly-distributed destination addresses and non-uniformly-distributed destination addresses. A simple new traffic model has been developed for generating non-uniformly-distributed destination addresses. This model is general enough to be used in developing new NoC architectures and captures universally accepted place-and-route methodologies. Simulation results are used to illustrate how the hardware resources of a modified Fat Tree NoC can be minimized without affecting the network performance. The performance of a NoC with regular Mesh topology was also evaluated for comparison with the modified Fat Tree topology.

A Routing Aggregation for Load Balancing Network-on-Chip

2015 ◽  
Vol 24 (09) ◽  
pp. 1550137 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu ◽  
Duan Zhou
Keyword(s):  
Load Balancing ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Long Distance ◽  
Link Utilization ◽  
Packet Latency ◽  
Overall Performance ◽  
Simulation Results ◽  
Routing Methods ◽  
On Chip

A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The computing nodes with dense traffic and long distance in network are gathered into the same routing node to form a super router. A load balancing routing algorithm for super router is presented to improve the overall performance of NoC. A simulation platform using System C is presented to confirm the feasibility of the proposed design in 2D mesh. The simulation results show that the proposed RA design can reduce the average packet latency and the standard deviation of host link utilization 8% and 33%, respectively compared with the reported routing methods. The area cost and power consumption compared with the reported schemes are 22% and 12% less, respectively.

RQRT: REDUCE QUERYING ROUTING TABLE FOR MESH-BASED NETWORK-ON-CHIP

2011 ◽  
Vol 20 (08) ◽  
pp. 1529-1545
Author(s):  
MINGHUA TANG ◽  
XIAOLA LIN
Keyword(s):  
Routing Algorithm ◽  
Packet Delay ◽  
Network On Chip ◽  
Average Packet Delay ◽  
Routing Table ◽  
Simulation Results ◽  
Pass Through ◽  
On Chip

Although using table to implement routing algorithm has some advantages in network-on-chip (NoC), the router queries the routing table whenever a packet is to be forwarded. The querying time significantly increases the packet delay even if some methods have been proposed to shorten the table size. In mesh-based NoC, statistics shows that two neighbor routers have the same routing options for over 50% packets, on average. In this paper, we propose a technique to let packets pass through some routers without querying the routing table. Consequently, the time to query the routing table is significantly decreased. Simulation results show that this leads up to 16% decrease of average packet delay.

AFRM: Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

2017 ◽  
Vol 26 (12) ◽  
pp. 1750200 ◽  
Author(s):  
Ruilian Xie ◽  
Jueping Cai ◽  
Peng Wang ◽  
Xin Zhang ◽  
Juan Wang
Keyword(s):  
Fault Tolerant ◽  
State Of The Art ◽  
High Reliability ◽  
Network Simulation ◽  
Network On Chip ◽  
Virtual Channels ◽  
Routing Method ◽  
Simulation Results ◽  
On Chip ◽  
2D Network

High reliability against undesirable effects is one of the key objectives in the design for Network-on-Chip (NoC). As a result, designing reliable and efficient routing method is highly desirable. This paper presents a novel turn model called NMad-y using one and two virtual channels along the [Formula: see text]- and [Formula: see text]-dimensions, respectively, and Adaptive and Fault-tolerant Routing Method (AFRM) which is designed based on the NMad-y turn model. AFRM can effectively tolerate multiple faulty routers and links in more complicated faulty situations by the link status of neighbor routers within two hops. AFRM is able to impose the reliability of network without losing the performance of network. Simulation results show that AFRM achieves better saturation throughput (0.83% on average) than a state-of-the-art fault-tolerant routing method and maintains high reliability of more than 97.43% on average.

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