Quadrature MC-DCSK Scheme for Chaos-Based Cognitive Radio

2019 ◽  
Vol 29 (13) ◽  
pp. 1950177 ◽  
Author(s):  
Nguyen Xuan Quyen

In this study, we investigate an enhanced architecture of multicarrier differential chaos-shift keying (MC-DCSK) scheme using quadrature modulation (QM), namely QMC-DCSK. The use of quadrature modulation aims at doubling the data rate over a defined bandwidth and hence improve bandwidth efficiency of the system. In the proposed scheme, the chaotic spreading sequence is transmitted on a predefined frequency while each of the remaining frequencies is phase-shifted at a [Formula: see text] angle in order to produce two quadrature subcarriers located at the same frequency. These subcarriers are modulated by the product of the chaotic spreading sequence and the corresponding bit substreams in parallel. Noncoherent demodulation is carried out in the receiver in order to recover the original data based on the sign of correlation values. Architecture and operation of the conventional and proposed schemes are described. The BER performance over a wireless channel is theoretically derived and then numerically verified. The bit rate, energy and bandwidth efficiencies are evaluated in comparison with those of MC-DCSK. In particular, the application of the proposed scheme to cognitive radio (CR) in the scenario of using multicarrier modulation and chaotic spread-spectrum is discussed and evaluated. The obtained results prove that QMC-DCSK is a fit technique for CR communications.

2017 ◽  
Vol 27 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Nguyen Xuan Quyen

The past decade has witnessed a boom of wireless communications which necessitate an increasing improvement of data rate, error-rate performance, bandwidth efficiency, and information security. In this work, we propose a quadrature (IQ) differential chaos-shift keying (DCSK) modulation scheme for the application in cognitive radio (CR), named CR-IQ-DCSK, which offers the above improvement. Chaotic signal is generated in frequency domain and then converted into time domain via an inverse Fourier transform. The real and imaginary components of the frequency-based chaotic signal are simultaneously used in in-phase and quadrature branches of an IQ modulator, where each branch conveys two bits by means of a DCSK-based modulation. Schemes and operating principle of the modulator and demodulator are proposed and described. Analytical BER performance for the proposed schemes over a typical multipath Rayleigh fading channel is derived and verified by numerical simulations. Results show that the proposed scheme outperforms DCSK, CDSK and performs better with the increment of the number of channel paths.


Author(s):  
Katyayani Kashayp ◽  
Kandarpa Kumar Sarma ◽  
Manash Pratim Sarma

Spread spectrum modulation (SSM) finds important place in wireless communication primarily due to its application in Code Division Multiple Access (CDMA) and its effectiveness in channels fill with noise like signals. One of the critical issues in such modulation is the generation of spreading sequence. This chapter presents a design of chaotic spreading sequence for application in a Direct Sequence Spread Spectrum (DS SS) system configured for a faded wireless channel. Enhancing the security of data transmission is a prime issue which can better be addressed with a chaotic sequence. Generation and application of chaotic sequence is done and a comparison with Gold sequence is presented which clearly indicates achieving better performance with simplicity of design. Again a multiplierless logistic map sequence is generated for lower power requirements than the existing one. The primary blocks of the system are implemented using Verilog and the performances noted. Experimental results show that the proposed system is an efficient sequence generator suitable for wideband systems demonstrating lower BER levels, computational time and power requirements compared to traditional LFSR based approaches.


2017 ◽  
Vol 27 (01) ◽  
pp. 1850008 ◽  
Author(s):  
Nguyen Xuan Quyen

A high-efficiency differential-chaos-shift-keying (HE-DCSK) system has been proposed previously for the improvement of both bit-rate and bit-error-rate (BER) performance in comparison with the conventional DCSK system. This improvement made HE-DCSK be a promising solution for chaos-based communications. However, the performance of this system was just investigated under an additive white Gaussian noise (AWGN) channel. This is main motivation for our work to evaluate the performance of HE-DCSK over a typical wireless channel which is simultaneously affected by white noise, fading, multipath, and delay spread. The operation of the transmitter and receiver over the wireless channel is modeled and described. The BER performance is evaluated by theoretical analysis using Gaussian approximation and discrete integration. The numerical results obtained by Monte Carlo simulations are presented to verify the analyzed performance. Obtained results point out that the HE-DCSK system not only performs better than other DCSK-based ones under wireless channels but also can exploit the multipath characteristic to improve the performance.


Author(s):  
Fadhil S. Hasan ◽  
Mahmood F. Mosleh ◽  
Aya H. Abdulhameed

<span lang="EN-US">Spread spectrum (SS) communications have attracted interest because of their channel attenuation immunity and low intercept potential. Apart from some extra features such as basic transceiver structures, chaotic communication would be the analog alternative to digital SS systems. Differential chaos shift keying (DCSK) systems, non-periodic and random characteristics among chaos carriers as well as their interaction with soft data are designed based on low-density parity-check (LDPC) codes in this brief. Because of simple structure, and glorious ability to <span>correct errors. Using the Xilinx kintex7 FPGA development kit, we investigate the hardware performance and resource requirement tendencies of the DCSK</span> communication system based on LDPC decoding algorithms (Prob. Domain, Log Domain and Min-Sum) over AWGN channel. The results indicate that the proposed system model has substantial improvements in the performance of the bit error rate (BER) and the real-time process. The Min-Sum decoder has relatively fewer FPGA resources than the other decoders. The implemented system will achieve 10-4 BER efficiency with 5 dB associate E<sub>b</sub>/N<sub>o</sub> as a coding gain.</span>


2021 ◽  
Vol 1804 (1) ◽  
pp. 012088
Author(s):  
Salsabeel S. Hasan ◽  
Zahir M. Hussain

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