Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature

2007 ◽  
Vol 46 (No. 49) ◽  
pp. L1228-L1230 ◽  
Author(s):  
Hyun-Jun Cho ◽  
Wan-Shick Hong ◽  
Sung-Hyun Lee ◽  
Tae-Hwan Kim ◽  
Kyung-Min Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Low Temperature ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Layer ◽  
Chemical Vapor ◽  
Gate Insulator ◽  
Catalytic Chemical Vapor Deposition

Low-Temperature Formation of SiNx Gate Insulator for Thin-Film Transistor Using CAT-CVD Method

1998 ◽  
Vol 508 ◽  
Author(s):  
A. Izumi ◽  
T. Ichise ◽  
H. Matsumura
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Silicon Nitride ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
State Density ◽  
Gate Insulator ◽  
Catalytic Chemical Vapor Deposition ◽  
Silicon Nitride Films

AbstractSilicon nitride films prepared by low temperatures are widely applicable as gate insulator films of thin film transistors of liquid crystal displays. In this work, silicon nitride films are formed around 300 °C by deposition and direct nitridation methods in a catalytic chemical vapor deposition system. The properties of the silicon nitride films are investigated. It is found that, 1) the breakdown electric field is over 9MV/cm, 2) the surface state density is about 1011cm−2eV−1 are observed in the deposition films. These result shows the usefulness of the catalytic chemical vapor deposition silicon nitride films as gate insulator material for thin film transistors.

Poly-SiGe TFTs Fabricated by Low Temperature Chemical Vapor Deposition at 450°C

2001 ◽  
Vol 686 ◽  
Author(s):  
Kousaku Shimizu ◽  
Jianjun Zhang ◽  
Jeong-woo Lee ◽  
Jun-ichi Hanna
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Low Temperature ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Gas Flow ◽  
Chemical Vapor ◽  
Polycrystalline Materials ◽  
Si Substrates ◽  
Vapor Deposition Technique

AbstractLow temperature growth of poly-SiGe has been investigated by reactive thermal chemical vapor deposition technique, which is a newly developed technique for preparing polycrystalline materials with using redox reactions in a set of source materials, Si2H6 and GeF4.. In order to prepare high uniformity and reproducibility of Si-rich poly-SiGe, total pressure, gas flow ratio, and residence time are optimized at 450°C of substrate temperature. Through optimizing the conditions, poly-Si1−xGex (x<0.04) films have been prepared in the reproducibility more than 90% and uniformity more than 88%. Bottom gate type of n-channel thin film transistors has been fabricated in various grain size of poly-Si1−xGex on SiO2 (100nm)/Si substrates. 5-36 cm2/Vs of field effect mobility of thin film transistors (L/W = 50μm/50μm) have been achieved after hydrogenation, whose threshold voltage is around 2±0.5V, and on/off ratio is more than 104.

scholarly journals A Phase Diagram for Morphology and Properties of Low Temperature Deposited Polycrystalline Silicon Grown by Hot-wire Chemical Vapor Deposition

2004 ◽  
Vol 808 ◽  
Author(s):  
Christine E. Richardson ◽  
Maribeth S. Mason ◽  
Harry A. Atwater
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Low Temperature ◽  
Vapor Deposition ◽  
Polycrystalline Silicon ◽  
Crystalline Silicon ◽  
Solid Phase ◽  
Chemical Vapor ◽  
High Energy ◽  
Hot Wire

ABSTRACTThe fabrication of low temperature polycrystalline silicon with lifetimes close to single crystalline silicon, but with internal surface passivation similar to that observed in deposited microcrystalline silicon, is a promising direction for thin film polycrystalline silicon photovoltaics. To achieve this, large grains with passivated grain boundaries and intragranular defects are required. We investigate the low-temperature (250-550°C) epitaxial growth of thin silicon films by hot-wire chemical vapor deposition (HWCVD) on Si(100) substrates and large-grained polycrystalline silicon template layers formed by selective nucleation and solid phase epitaxy (SNSPE). Using reflection high energy electron diffraction (RHEED) and transmission electron microscopy (TEM), we have observed epitaxial, twinned epitaxial, mixed epitaxial/polycrystalline and polycrystalline phases in the 50 nm–15 μm thickness regime. HWCVD growth on Si(100) was performed using a mixture of diluted silane (4% in He) and hydrogen at a H2/SiH4 ratio of 50:1 at substrate temperatures from 300–475°C. We will discuss the relationship between the microstructure and photoconductive decay lifetimes of these undoped layers on Si(100) and SNSPE templates as well as their suitability for use in thin-film photovoltaic applications.

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