Nanoscale CMOS circuit leakage power reduction by double-gate device

Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04 ◽

10.1145/1013235.1013267 ◽

2004 ◽

Author(s):

Keunwoo Kim ◽

Koushik K. Das ◽

Rajiv V. Joshi ◽

Ching-Te Chuang

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Double Gate ◽

Cmos Circuit ◽

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Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Proceedings of the great lakes symposium on VLSI - GLSVLSI '12 ◽

10.1145/2206781.2206811 ◽

2012 ◽

Author(s):

Jing Yang ◽

Yong-bin Kim

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Cmos Circuit ◽

Nanoscale Cmos ◽

Body Biasing ◽

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Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

International Journal of Engineering Trends and Technology ◽

10.14445/22315381/ijett-v46p254 ◽

2017 ◽

Vol 46 (6) ◽

pp. 309-315

Author(s):

P Prashanti ◽

◽

A.Shra vya ◽

K.Dhruthi Vasista ◽

U.Pran athi ◽

...

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Technology Scaling ◽

Nanoscale Cmos ◽

Reduction Techniques ◽

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A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

International Journal of Computer Applications ◽

10.5120/ijca2017915459 ◽

2017 ◽

Vol 173 (10) ◽

pp. 26-31

Author(s):

Chandra Pratap ◽

Laxmi Kumre

Keyword(s):

Power Reduction ◽

Leakage Power ◽

New Technique ◽

Cmos Circuit ◽

A New Technique

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A novel leakage power reduction technique for CMOS circuit design

2010 International SoC Design Conference ◽

10.1109/socdc.2010.5682957 ◽

2010 ◽

Author(s):

Jae Woong Chun ◽

C. Y. Roger Chen

Keyword(s):

Circuit Design ◽

Power Reduction ◽

Leakage Power ◽

Reduction Technique ◽

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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2010.2044710 ◽

2010 ◽

Vol 59 (5) ◽

pp. 1127-1133 ◽

Author(s):

HeungJun Jeon ◽

Yong-Bin Kim ◽

Minsu Choi

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Reduction Technique ◽

Nanoscale Cmos ◽

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LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.2.14291 ◽

2018 ◽

Vol 6 (2) ◽

pp. 1

Author(s):

SEKHAR REDDY M. CHANDRA ◽

REDDY P. RAMANA ◽

◽

Keyword(s):

Power Reduction ◽

Leakage Power ◽

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Effect of leakage power reduction techniques on combinational circuits

2015 Online International Conference on Green Engineering and Technologies (IC-GET) ◽

10.1109/get.2015.7453862 ◽

2015 ◽

Author(s):

M. Manoranjani ◽

T. Ravi ◽

R. Ramya

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Combinational Circuits ◽

Reduction Techniques

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Exploring the limits of leakage power reduction in caches

ACM Transactions on Architecture and Code Optimization ◽

10.1145/1089008.1089009 ◽

2005 ◽

Vol 2 (3) ◽

pp. 221-246 ◽

Author(s):

Yan Meng ◽

Timothy Sherwood ◽

Ryan Kastner

Keyword(s):

Power Reduction ◽

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Leakage power reduction in CMOS modulo4 adder and modulo4 multiplier in sub-micron technology

International Conference on Sustainable Energy and Intelligent Systems (SEISCON 2011) ◽

10.1049/cp.2011.0430 ◽

2011 ◽

Author(s):

M.J. Rani ◽

S. Malarkkan

Keyword(s):

Power Reduction ◽

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Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors

2009 15th IEEE Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2009.11 ◽

2009 ◽

Author(s):

Masashi Imai ◽

Kouei Takada ◽

Takashi Nanya

Keyword(s):

Threshold Voltage ◽

Reduction Method ◽

Power Reduction ◽

Leakage Power ◽

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