Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

2017 ◽  
Vol 46 (6) ◽  
pp. 309-315
Author(s):  
P Prashanti ◽  
◽  
A.Shra vya ◽  
K.Dhruthi Vasista ◽  
U.Pran athi ◽  
...  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Technology Scaling ◽  
Nanoscale Cmos ◽  
Reduction Techniques ◽  
Cmos Vlsi

Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit

2020 ◽  
Vol 12 (10) ◽  
pp. 1289-1295
Author(s):  
Suruchi Sharma ◽  
Santosh Kumar ◽  
Alok Kumar Mishra ◽  
D. Vaithiyanathan ◽  
Baljit Kaur
Keyword(s):  
Supply Voltage ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Leakage Currents ◽  
Systematic Analysis ◽  
Technology Scaling ◽  
Reduction Techniques ◽  
Benchmark Circuit ◽  
Pvt Variations ◽  
Cmos Vlsi

High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reduction techniques at the circuit level, such as Power Gating (PG), Drain Gating (DG), LECTOR and GALEOR, and analyzes the effect of PVT variations on the dissipation and delay of leakage power using the ISCAS C17 benchmark circuit.

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits

2012 ◽  
Vol 55 (8) ◽  
pp. 42-48 ◽  
Author(s):  
Pushpa Saini ◽  
Rajesh Mehra
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Cmos Vlsi
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