Low power gate-level design with mixed-V th (MVT) techniques

2004 ◽  
Author(s):  
Frank Sill ◽  
Frank Grassert ◽  
Dirk Timmermann
Keyword(s):  
Low Power ◽  
Level Design

scholarly journals Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

2019 ◽  
Vol 13 (7) ◽  
pp. 1063-1070
Author(s):  
Ramaian Subramanian Kamalakannan ◽  
Kuppusamy Venkatachalam
Keyword(s):  
Low Power ◽  
Clock Gating ◽  
Level Design ◽  
Power Radiation

scholarly journals Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

2019 ◽  
Vol 36 (6) ◽  
pp. 97-110 ◽  
Author(s):  
Bipin Rajendran ◽  
Abu Sebastian ◽  
Michael Schmuker ◽  
Narayan Srinivasa ◽  
Evangelos Eleftheriou
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
System Level ◽  
System Level Design ◽  
Neuromorphic Hardware ◽  
Level Design
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