Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only)

2010 ◽  
Author(s):  
Shaoshan Liu ◽  
Richard Neil Pittman ◽  
Alessandro Forin
Keyword(s):  
Partial Reconfiguration ◽  
Reconfiguration Overhead

A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration

2012 ◽  
Vol 433-440 ◽  
pp. 5172-5177
Author(s):  
Xiao Jing Feng ◽  
Xi Li ◽  
Wang Chao ◽  
Xue Hai Zhou ◽  
Jun Neng Zhang
Keyword(s):  
Embedded Systems ◽  
Hardware Design ◽  
Design Flow ◽  
Experimental Results ◽  
Prototype System ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Software And Hardware ◽  
Reconfiguration Overhead ◽  
Hardware Designs

The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.

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