scholarly journals Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration

2020 ◽  
Author(s):  
Chen Wu ◽  
Mingyu Wang ◽  
Xinyuan Chu ◽  
Kun Wang ◽  
Lei He
Keyword(s):  
High Performance ◽  
Floating Point ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

scholarly journals Numerical algorithms for high-performance computational science

2020 ◽  
Vol 378 (2166) ◽  
pp. 20190066 ◽  
Author(s):  
Jack Dongarra ◽  
Laura Grigori ◽  
Nicholas J. Higham
Keyword(s):  
High Performance ◽  
Numerical Algorithms ◽  
Computational Science ◽  
Floating Point ◽  
Important Criterion ◽  
Data Movement ◽  
Floating Point Arithmetic ◽  
High Performance Computers ◽  
Point Arithmetic ◽  
Speed And Accuracy

A number of features of today’s high-performance computers make it challenging to exploit these machines fully for computational science. These include increasing core counts but stagnant clock frequencies; the high cost of data movement; use of accelerators (GPUs, FPGAs, coprocessors), making architectures increasingly heterogeneous; and multi- ple precisions of floating-point arithmetic, including half-precision. Moreover, as well as maximizing speed and accuracy, minimizing energy consumption is an important criterion. New generations of algorithms are needed to tackle these challenges. We discuss some approaches that we can take to develop numerical algorithms for high-performance computational science, with a view to exploiting the next generation of supercomputers. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

2019 ◽  
Vol 27 (8) ◽  
pp. 1874-1885 ◽  
Author(s):  
Xiaocong Lian ◽  
Zhenyu Liu ◽  
Zhourui Song ◽  
Jiwu Dai ◽  
Wei Zhou ◽  
...  
Keyword(s):  
High Performance ◽  
Floating Point ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

scholarly journals Fuzzy Processing Implementation in Dedicated Digital Hardware

2010 ◽  
Vol 56 (4) ◽  
pp. 405-410 ◽  
Author(s):  
Przemysław Szecówka ◽  
Adam Musiał
Keyword(s):  
Fuzzy Sets ◽  
High Performance ◽  
Digital Circuit ◽  
Synchronous Machine ◽  
Floating Point ◽  
Weighted Sum ◽  
Sample Design ◽  
Floating Point Arithmetic ◽  
Digital Hardware ◽  
Point Arithmetic

Fuzzy Processing Implementation in Dedicated Digital HardwareThe paper presents a concept of digital circuit dedicated for fuzzy processing with numerical inputs and outputs. Partially concurrent and pipelined data flow provides high performance, with relatively low dependence on particular algorithm complexity. Sample design with triangular fuzzy sets, rule strength calculation (minimumapproach) and defuzzyfication by weighted sum of fuzzy sets centers was implemented in VHDL, verified and synthesized for FPGA. Floating point arithmetic was applied, including dvision performed by dedicated synchronous machine. All modules were prepared for easy reuse/redesign.

scholarly journals Mixed-precision iterative refinement using tensor cores on GPUs to accelerate solution of linear systems

2020 ◽  
Vol 476 (2243) ◽  
pp. 20200110
Author(s):  
Azzam Haidar ◽  
Harun Bayraktar ◽  
Stanimire Tomov ◽  
Jack Dongarra ◽  
Nicholas J. Higham
Keyword(s):  
Linear Systems ◽  
Numerical Stability ◽  
High Performance ◽  
Iterative Refinement ◽  
Floating Point ◽  
Double Precision ◽  
Floating Point Arithmetic ◽  
Mixed Precision ◽  
Scientific Simulations ◽  
Point Arithmetic

Double-precision floating-point arithmetic (FP64) has been the de facto standard for engineering and scientific simulations for several decades. Problem complexity and the sheer volume of data coming from various instruments and sensors motivate researchers to mix and match various approaches to optimize compute resources, including different levels of floating-point precision. In recent years, machine learning has motivated hardware support for half-precision floating-point arithmetic. A primary challenge in high-performance computing is to leverage reduced-precision and mixed-precision hardware. We show how the FP16/FP32 Tensor Cores on NVIDIA GPUs can be exploited to accelerate the solution of linear systems of equations Ax  =  b without sacrificing numerical stability. The techniques we employ include multiprecision LU factorization, the preconditioned generalized minimal residual algorithm (GMRES), and scaling and auto-adaptive rounding to avoid overflow. We also show how to efficiently handle systems with multiple right-hand sides. On the NVIDIA Quadro GV100 (Volta) GPU, we achieve a 4 × − 5 × performance increase and 5× better energy efficiency versus the standard FP64 implementation while maintaining an FP64 level of numerical stability.

Sign in / Sign up

Export Citation Format

Share Document