Detecting Malicious Switches for a Secure Software-defined Tactile Internet

2021 ◽  
Vol 21 (4) ◽  
pp. 1-23
Author(s):  
Bin Yuan ◽  
Chen Lin ◽  
Deqing Zou ◽  
Laurence Tianruo Yang ◽  
Hai Jin

The rapid development of the Internet of Things has led to demand for high-speed data transformation. Serving this purpose is the Tactile Internet, which facilitates data transfer in extra-low latency. In particular, a Tactile Internet based on software-defined networking (SDN) has been broadly deployed because of the proven benefits of SDN in flexible and programmable network management. However, the vulnerabilities of SDN also threaten the security of the Tactile Internet. Specifically, an SDN controller relies on the network status (provided by the underlying switches) to make network decisions, e.g., calculating a routing path to deliver data in the Tactile Internet. Hence, the attackers can compromise the switches to jeopardize the SDN and further attack Tactile Internet systems. For example, an attacker can compromise switches to launch distributed denial-of-service attacks to overwhelm the SDN controller, which will disrupt all the applications in the Tactile Internet. In pursuit of a more secure Tactile Internet, the problem of abnormal SDN switches in the Tactile Internet is analyzed in this article, including the cause of abnormal switches and their influences on different network layers. Then we propose an approach that leverages the messages sent by all switches to identify abnormal switches, which adopts a linear structure to store historical messages at a relatively low cost. By mapping each flow message to the flow establishment model, our method can effectively identify malicious SDN switches in the Tactile Internet and thus enhance its security.

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Sicong Wang ◽  
Chen Wei ◽  
Yuanhua Feng ◽  
Hongkun Cao ◽  
Wenzhe Li ◽  
...  

AbstractAlthough photonics presents the fastest and most energy-efficient method of data transfer, magnetism still offers the cheapest and most natural way to store data. The ultrafast and energy-efficient optical control of magnetism is presently a missing technological link that prevents us from reaching the next evolution in information processing. The discovery of all-optical magnetization reversal in GdFeCo with the help of 100 fs laser pulses has further aroused intense interest in this compelling problem. Although the applicability of this approach to high-speed data processing depends vitally on the maximum repetition rate of the switching, the latter remains virtually unknown. Here we experimentally unveil the ultimate frequency of repetitive all-optical magnetization reversal through time-resolved studies of the dual-shot magnetization dynamics in Gd27Fe63.87Co9.13. Varying the intensities of the shots and the shot-to-shot separation, we reveal the conditions for ultrafast writing and the fastest possible restoration of magnetic bits. It is shown that although magnetic writing launched by the first shot is completed after 100 ps, a reliable rewriting of the bit by the second shot requires separating the shots by at least 300 ps. Using two shots partially overlapping in space and minimally separated by 300 ps, we demonstrate an approach for GHz magnetic writing that can be scaled down to sizes below the diffraction limit.


2012 ◽  
Vol 459 ◽  
pp. 544-548 ◽  
Author(s):  
Wei Liang ◽  
Jian Bo Xu ◽  
Wei Hong Huang ◽  
Li Peng

Network security technology ensures secure data transmission in network. Meanwhile, it brings extra overhead of security system in terms of cost and performance, which seriously affects the rapid development of existing high-speed encryption systems. The existing encryption technology cannot meet the demand of high security, low cost and high real-time. For solving above problems, an ECC encryption engine architecture based on scalable public key cipher and a high-speed configurable multiplication algorithm are designed. The algorithm was tested on FPGA platform and the experiment results show that the system has better computation speed and lower cost overhead. By comparing with other systems, our system has benefits in terms of hardware overhead and encryption time ratio


2005 ◽  
Vol 50 (12) ◽  
pp. 2065-2069 ◽  
Author(s):  
R. Marquez ◽  
E. Altman ◽  
S. Sole-Alvarez

2007 ◽  
Vol 1054 ◽  
Author(s):  
Ruth Houbertz ◽  
Herbert Wolter ◽  
Volker Schmidt ◽  
Ladislav Kuna ◽  
Valentin Satzinger ◽  
...  

ABSTRACTThe integration of optical interconnects in printed circuit boards (PCB) is a rapidly growing field worldwide due to a continuously increasing need for high-speed data transfer. There are any concepts discussed, among which are the integration of optical fibers or the generation of waveguides by UV lithography, embossing, or direct laser writing. The devices presented so far require many different materials and process steps, but particularly also highly-sophisticated assembly steps in order to couple the optoelectronic elements to the generated waveguides. In order to overcome these restrictions, an innovative approach is presented which allows the embedding of optoelectronic components and the generation of optical waveguides in only one optical material. This material is an inorganic-organic hybrid polymer, in which the waveguides are processed by two-photon absorption (TPA) processes, initiated by ultra-short laser pulses. In particular, due to this integration and the possibility ofin situpositioning the optical waveguides with respect to the optoelectronic components by the TPA process, no complex packaging or assembly is necessary. Thus, the number of necessary processing steps is significantly reduced, which also contributes to the saving of resources such as energy or solvents. The material properties and the underlying processes will be discussed with respect to optical data transfer in PCBs.


2012 ◽  
Vol 229-231 ◽  
pp. 1543-1546
Author(s):  
Xiao Bo Zhou ◽  
Min Xia ◽  
Hai Long Cheng

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.


2012 ◽  
Vol 468-471 ◽  
pp. 920-923
Author(s):  
Ya Ping Bao ◽  
Li Liu ◽  
Yuan Wang ◽  
Qian Song

This paper introduced a fast fingerprint identification system based on TMS320VC5416 DSP chip and MBF200 solidity fingerprint sensor. It precipitates fingerprint identification device developing into the direction of miniaturization, embedded and automatic.It recommends fingerprint identification system hardware and software design and the main system processing flow, aim at fingerprint identification arithmetic, the influence of system operation speed is being researched at the same time. High-speed data acquisition system is been built in order to achieve a DSP fingerprint identification system with high efficiency and low cost.


Author(s):  
Ivan Mozghovyi ◽  
Anatoliy Sergiyenko ◽  
Roman Yershov

Increasing requirements for data transfer and storage is one of the crucial questions now. There are several ways of high-speed data transmission, but they meet limited requirements applied to their narrowly focused specific target. The data compression approach gives the solution to the problems of high-speed transfer and low-volume data storage. This paper is devoted to the compression of GIF images, using a modified LZW algorithm with a tree-based dictionary. It has led to a decrease in lookup time and an increase in the speed of data compression, and in turn, allows developing the method of constructing a hardware compression accelerator during the future research.


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