scholarly journals GIF IMAGE HARDWARE COMPRESSORS

2021 ◽  
Author(s):  
Ivan Mozghovyi ◽  
Anatoliy Sergiyenko ◽  
Roman Yershov
Keyword(s):  
Data Compression ◽  
Data Storage ◽  
High Speed ◽  
Data Transfer ◽  
Future Research ◽  
Volume Data ◽  
High Speed Data ◽  
Lzw Algorithm ◽  
And Storage ◽  
Speed Data Transmission

Increasing requirements for data transfer and storage is one of the crucial questions now. There are several ways of high-speed data transmission, but they meet limited requirements applied to their narrowly focused specific target. The data compression approach gives the solution to the problems of high-speed transfer and low-volume data storage. This paper is devoted to the compression of GIF images, using a modified LZW algorithm with a tree-based dictionary. It has led to a decrease in lookup time and an increase in the speed of data compression, and in turn, allows developing the method of constructing a hardware compression accelerator during the future research.

scholarly journals A Signal Amplification-based Transceiver for Visible Light Communication

2020 ◽  
Vol 26 (11) ◽  
pp. 123-132
Author(s):  
Augustus Ehiremen Ibhaze ◽  
Frederick O Edeko ◽  
Patience E Orukpe
Keyword(s):  
Visible Light ◽  
Data Transmission ◽  
High Speed ◽  
Data Transfer ◽  
Visible Light Communication ◽  
Wireless Technology ◽  
Capacity Enhancement ◽  
Large Bandwidth ◽  
High Speed Data ◽  
Speed Data Transmission

Visible light communication (VLC) is an upcoming wireless technology for next-generation communication for high-speed data transmission. It has the potential for capacity enhancement due to its characteristic large bandwidth. Concerning signal processing and suitable transceiver design for the VLC application, an amplification-based optical transceiver is proposed in this article. The transmitter consists of a driver and laser diode as the light source, while the receiver contains a photodiode and signal amplifying circuit. The design model is proposed for its simplicity in replacing the trans-impedance and transconductance circuits of the conventional modules by a simple amplification circuit and interface converter. The system was tested at communication distances of 1m and 3.5m using a terminal emulation program for data transfer between two computing devices.

Design and Realization of High Speed Data Transmission Based on PCI Bus of DM642

2012 ◽  
Vol 433-440 ◽  
pp. 3688-3691
Author(s):  
Bao Feng Zhang ◽  
Xiao Kun Chang
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Data Transfer ◽  
Pci Bus ◽  
Bus Driver ◽  
Data Acquisition Card ◽  
High Speed Data ◽  
Transfer Method ◽  
Windows Xp ◽  
Speed Data Transmission

For realizing data acquisition and transmission based on PCI bus, a device driver was designed for data acquisition card, which use TMS320DM642 of TI and it’s PCI interface as transfer protocol. And in this development, we use VC++6.0, DDK and DriverStudio3.2 to develop the PCI bus driver for Windows XP, and realizing DMA high-speed data transfer method between data acquisition card and computer RAM.

scholarly journals Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array)

2019 ◽  
Vol 9 (1) ◽  
pp. 65
Author(s):  
Nia Gella Augoestien ◽  
Ryan Aditya
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Clock Cycle ◽  
Computational Time ◽  
Storage Process ◽  
Cyclic Redundancy Check ◽  
Field Programmable ◽  
High Speed Data ◽  
And Storage ◽  
Speed Data Transmission

  Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process. When CRC is implemented using embedded software or processor, CRC requires many clock cycles. If CRC Generator implemented in special dedicated hardware, computational time reduced so that it can be met the high speed system communication requirement. This paper propose the design and implementation of CRC generator on FPGA that capable to minimaze computational time. The method is to reduce calculation latency by separating the coefficients of certain digits and calculating directly the result of  polinomial key modulo. CRC Generator in this paper was implemented on Xilinx Spartan®-6 Series (XC6LX16-CS324). The modeling results have succeeded  to finish computation on 1 clock cycle. Hardware eficiency is achieved 0.38 Gbps/Slice, while the throughput is 3,758 Gbps.

Integrated Instrument of Ultra-High Speed Data Acquisition and Storage

2012 ◽  
Vol 198-199 ◽  
pp. 1126-1131
Author(s):  
Jie Tao Diao ◽  
Yi Nan Wang ◽  
Zhao Lin Sun ◽  
Qing Jiang Li ◽  
Jin Ling Xing ◽  
...  
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Rapid Development ◽  
Storage System ◽  
Ultra High Speed ◽  
Design Structure ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
And Storage ◽  
Speed Data Transmission

Along with the rapid development of computer technology, high speed data acquisition and storage system has been widely applied in plenty of engineering fields, such as radar, aerospace industry, communication, etc. In order to satisfy the increasing requirement, we present the design structure of a novel integrated instrument for ultra-high speed data acquisition and storage, which is composed of ultra-high speed data acquisition, high speed data transmission and solid storage three main sub-systems. The detailed design and realization of the sub-systems are presented. We test and analysis the performance of the integrated instrument and the actual results show that the instrument performs stably and provides excellent speed and precision.

scholarly journals Industrial Internet of Things - Control of Industry Simulation Through Different Protocols

2021 ◽  
Vol 2115 (1) ◽  
pp. 012011
Author(s):  
P Surya ◽  
Asuman Suenbuel ◽  
Arockia Selvakumar Arockia Doss
Keyword(s):  
Internet Of Things ◽  
High Speed ◽  
Data Transfer ◽  
Research Work ◽  
Industrial Internet Of Things ◽  
Industrial Internet ◽  
High Speed Data ◽  
Single Data ◽  
Smart Technologies ◽  
Speed Data Transmission

Abstract In past few years there is a great demand for internet of things (IoT), It has become an important part of smart technologies. There have been many researches going-on in internet of things in both academics and industries. IoT using in industries is also known as Industrial Internet of Things (IIoT). Where smart sensors are used along with IoT are used. This research work is done to identify the best protocol for high-speed data transmission with no loss of data to prevent command lag between mobile controller and industry. In this research a soda filling Industry simulation with 3 different plants was controlled through a mobile application through different protocols with 4 different features of data transfer. The time of data sending and receiving from application and ESP32 controller are stored in a log. The speed of data transfer of all different protocols is compared. From the final result, ThingSpeak is an optimum protocol for this application which is 36% faster than HTTP in single data transfer and 39% faster than MQTT in continuous data transfer.

scholarly journals Design and Implementation of a Lossless Serial High-Speed Data Compression System

2011 ◽  
pp. 1-4
Author(s):  
J. Sunil Kumar ◽  
G. Mahesh Kumar
Keyword(s):  
Data Compression ◽  
High Speed ◽  
Parallel Architecture ◽  
Vlsi Architecture ◽  
Data Networks ◽  
Compression Performance ◽  
High Data ◽  
High Speed Data ◽  
High Space ◽  
And Storage

The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the X-Match algorithm. This design involves important trade off that affects the compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware. This device typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbits/s data networks and storage applications where it can double the performance of the original systems. To get high compression rate or to get high data rate of communication not restriction to follow the parallel architecture of data compression. By using existing method the main draw backs are 1. Variation in compression 2. Throughput, 3.Latency, 4.High space, 5. High power. So by using this proposed method we can reduce the variation in the compression, latency and increase through put. And this novel VLSI architecture has a power consumption of 81mwatts power

Analysis of Inter-Satellite Optical Wireless Communication System

2017 ◽  
Vol 7 (10) ◽  
pp. 10
Author(s):  
Rajbir Singh
Keyword(s):  
Wireless Communication ◽  
Optical Networks ◽  
Data Transmission ◽  
High Speed ◽  
Open Space ◽  
Communication Link ◽  
Optical Wireless Communication ◽  
Optical Wireless ◽  
High Speed Data ◽  
Speed Data Transmission

Optical networks are bandwidth efficient networks are used for long haul communication providing seamless data transfer. For high speed data transmission in open space between different satellites, Inter-satellite Optical wireless communication (IsOWC) is widely used .In this paper we have evaluated the performance of IsOWC communication link for high speed data transmission .The performance of the system is evaluated on the basis of qualitative parameters such as Q-factor and BER using optisystem simulator.

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