scholarly journals Physics-inspired heuristics for soft MIMO detection in 5G new radio and beyond

Author(s):  
Minsung Kim ◽  
Salvatore Mandrà ◽  
Davide Venturelli ◽  
Kyle Jamieson
Keyword(s):  
Author(s):  
Shihab Jimaa ◽  
Jawahir Al-Ali

Background: The 5G will lead to a great transformation in the mobile telecommunications sector. Objective: The huge challenges being faced by wireless communications such as the increased number of users have given a chance for 5G systems to be developed and considered as an alternative solution. The 5G technology will provide a higher data rate, reduced latency, more efficient power than the previous generations, higher system capacity, and more connected devices. Method: It will offer new different technologies and enhanced versions of the existing ones, as well as new features. 5G systems are going to use massive MIMO (mMIMO), which is a promising technology in the development of these systems. Furthermore, mMIMO will increase the wireless spectrum efficiency and improve the network coverage. Result: In this paper we present a brief survey on 5G and its technologies, discuss the mMIMO technology with its features and advantages, review the mMIMO capacity and energy efficiency and also presents the recent beamforming techniques. Conclusion: Finally, simulation of adopting different mMIMO detection algorithms are presented, which shows the alternating direction method of multipliers (ADMM)-based infinity-norm (ADMIN) detector has the best performance.


2017 ◽  
Vol 55 (6) ◽  
pp. 64-71 ◽  
Author(s):  
Shao-Yu Lien ◽  
Shin-Lin Shieh ◽  
Yenming Huang ◽  
Borching Su ◽  
Yung-Lin Hsu ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.


Author(s):  
Takumi Takahashi ◽  
Antti Tolli ◽  
Shinsuke Ibi ◽  
Seiichi Sampei

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.


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