Analysis and Test of PCB via Hole Heat Dissipation Performance in Circuit Practice Course

Author(s):  
Min Wang ◽  
Mengrou Feng ◽  
Xikun Lu ◽  
Ran Wei
Keyword(s):  
Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 650 ◽  
Author(s):  
Shengjun Zhou ◽  
Haohao Xu ◽  
Mengling Liu ◽  
Xingtong Liu ◽  
Jie Zhao ◽  
...  

We demonstrated two types of GaN-based flip-chip light-emitting diodes (FCLEDs) with distributed Bragg reflector (DBR) and without DBR to investigate the effect of dielectric TiO2/SiO2 DBR on optical and electrical characteristics of FCLEDs. The reflector consisting of two single TiO2/SiO2 DBR stacks optimized for different central wavelengths demonstrates a broader reflectance bandwidth and a less dependence of reflectance on the incident angle of light. As a result, the light output power (LOP) of FCLED with DBR shows 25.3% higher than that of FCLED without DBR at 150 mA. However, due to the better heat dissipation of FCLED without DBR, it was found that the light output saturation current shifted from 268 A/cm2 for FCLED with DBR to 296 A/cm2 for FCLED without DBR. We found that the use of via-hole-based n-type contacts can spread injection current uniformly over the entire active emitting region. Our study paves the way for application of DBR and via-hole-based n-type contact in high-efficiency FCLEDs.


2009 ◽  
Vol E92-C (2) ◽  
pp. 239-246 ◽  
Author(s):  
Keiko ODA ◽  
Takahiro MATSUBARA ◽  
Kei-ichiro WATANABE ◽  
Kaori TANAKA ◽  
Maraki MAETANI

2021 ◽  
Vol 33 (1) ◽  
pp. 012029
Author(s):  
Stefan Polenz ◽  
Christian Kolbe ◽  
Florian Bittner ◽  
Elena López ◽  
Frank Brückner ◽  
...  

Author(s):  
Ian Kearney ◽  
Stephen Brink

Abstract The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.


2011 ◽  
Vol 30 (8) ◽  
pp. 2029-2032
Author(s):  
Yong Han ◽  
Yan-wen Liu ◽  
Yao-gen Ding ◽  
Pu-kun Liu ◽  
Chun-hua Lu ◽  
...  
Keyword(s):  

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