Design and Implementation of FSM Based MBIST using March Algorithm

The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.

The Development of an EVB Socket Solution for Automotive Mixed-Signal ICs

Failure analysis on mixed-signal ICs for automotive applications often requires the use of EVBs (evaluation boards) to replicate the failure mode. Typically, automotive ICs are used in conjunction with other components to create automotive modules, such as; PCM (power-train control modules), ECU (engine control units), TCU (transmission control units), etc. EVBs are used to replicate module level functionality, as well as reproduce ATE (automatic test equipment) tests required for analysis. An integral part of EVB design, functionality and performance is related to the IC socket, which is the direct interface between the IC and the EVB. See Figure 1. EVB socket solutions will vary based on the required analysis (backside / topside analysis), package type and IC functionality.

Measurement applications in Industry 4.0: the case of an IoT–oriented platform for remote programming of automatic test equipment

<p><span lang="EN-GB">A laboratory regarded as a site that collects IoT devices, and which allows remote clients to use them as an automatic test equipment (ATE) through a controller acting as service provider, is proposed herein. To assure efficiency and responsiveness, the controller is programmed as a multithreading system that takes advantage of multicore processors. The controller includes a server application that supports communication with clients by means of a TCP/IP protocol. It uses GPIB bus functionalities to control the instruments of the local ATE. It allows several clients to connect and interact with the specific resources of the laboratory. Thanks to the availability of identical sets of resources and to the underlying multithreading philosophy, client requests are processed in tandem rather than according to a classical queuing approach.</span></p><p><span lang="EN-GB"><br /></span></p>