Early error detection in syntax-driven parsers

1986 ◽  
Vol 30 (6) ◽  
pp. 617-626 ◽  
Author(s):  
A. V. Moura
Keyword(s):  
Author(s):  
María Magdalena Añino ◽  
Gabriela Merino ◽  
Alberto Miyara ◽  
Marisol Perassi ◽  
Emiliano Ravera ◽  
...  

2021 ◽  
Vol 38 (1) ◽  
pp. 159-168
Author(s):  
SIMONA MOTOGNA ◽  
◽  
DIANA CRISTEA ◽  
DIANA ȘOTROPA MOLNAR ◽  
◽  
...  

Tools that focus on static code analysis for early error detection are of utmost importance in software development, especially since the propagation of errors is strongly related to higher costs in the development process. Formal Concept Analysis is a prominent field of applied mathematics that uses conceptual landscapes to discover and represent maximal clusters of data. Its expressive visualization method makes it suitable for exploratory analyses in different fields. In this paper we present a Formal Concept Analysis framework for static code analysis that can serve as a model for quantitative and qualitative exploration and interpretation of such results.


2011 ◽  
Vol 20 (08) ◽  
pp. 1505-1527 ◽  
Author(s):  
ZORAN STAMENKOVIĆ

The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.


2022 ◽  
Vol 72 (1) ◽  
pp. 40-48
Author(s):  
K.H. Kochaleema ◽  
G. Santhosh Kumar

This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML Statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation.


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