Achieving High Minority Carrier Lifetime through Low-Temperature a-Si:H Deposition and High-Temperature Anneal for Silicon Heterojunction Solar Cell Applications

ABSTRACTThis paper details the development of a technique to improve the minority carrier lifetime of 4H-SiC thick (≥ 100 μm) n-type epitaxial layers through multiple thermal oxidations. A steady improvement in lifetime is seen with each oxidation step, improving from a starting ambipolar carrier lifetime of 1.09 µs to 11.2 µs after 4 oxidation steps and a high-temperature anneal. This multiple-oxidation lifetime enhancement technique is compared to a single high-temperature oxidation step, and a carbon implantation followed by a high-temperature anneal, which are traditional ways to achieve high ambipolar lifetime in 4H-SiC n-type epilayers. The multiple oxidation treatment resulted in a high minimum carrier lifetime of 6 µs, compared to < 2 µs for other treatments. The implications of lifetime enhancement to high-voltage/high-current 4H-SiC power devices are also discussed.

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Hydrogen Plasma Post-Deposition Treatment for Passivation of a-Si/c-Si Interface for Heterojunction Solar Cell by Correlating Optical Emission Spectroscopy and Minority Carrier Lifetime

2017 IEEE 44th Photovoltaic Specialist Conference (PVSC) ◽

10.1109/pvsc.2017.8366194 ◽

2017 ◽

Cited By ~ 1

Author(s):

Anishkumar Soman ◽

Ugochukwu Nsofor ◽

Lei Zhang ◽

Ujjwal Das ◽

Tingyi Gu ◽

...

Keyword(s):

Solar Cell ◽

Emission Spectroscopy ◽

Optical Emission Spectroscopy ◽

Carrier Lifetime ◽

Minority Carrier ◽

Hydrogen Plasma ◽

Optical Emission ◽

Minority Carrier Lifetime ◽

Heterojunction Solar Cell ◽

Post Deposition

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Influence of Surface Morphology on the Effective Lifetime and Performance of Silicon Heterojunction Solar Cell

International Journal of Photoenergy ◽

10.1155/2015/273615 ◽

2015 ◽

Vol 2015 ◽

pp. 1-8 ◽

Cited By ~ 6

Author(s):

Shui-Yang Lien ◽

Yun-Shao Cho ◽

Yan Shao ◽

Chia-Hsun Hsu ◽

Chia-Chi Tsou ◽

...

Keyword(s):

Solar Cell ◽

Surface Morphology ◽

Carrier Lifetime ◽

Minority Carrier ◽

Short Circuit ◽

Turning Points ◽

Minority Carrier Lifetime ◽

Heterojunction Solar Cell ◽

Etching Time ◽

Effective Lifetime

Different etching times are used to etch silicon wafers. Effects of surface morphology on wafer minority carrier lifetime, passivation quality, and heterojunction solar cell (HJ) performance are investigated. The numbers of mountains and valleys, defined as turning points, on wafer surfaces are used to explain the minority carrier lifetime variations. For a wafer with a smaller amount of turning points, hydrogenated amorphous silicon (a-Si:H) passivation quality can be comparable to ideal iodine-ethanol solution passivation. If the wafer has a notable amount of turning points, the carrier lifetime decreases as the a-Si:H layer will not be able to be well-deposited on turning points. Furthermore, the PC1D simulation indicates that an optimal device conversion efficiency of 21.94% can be achieved at an etching time of 60 min, where a best combination of short-circuit current and open-circuit voltage is obtained.

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Application of minority carrier lifetime monitor in heterojunction solar cell production

Scientia Sinica Technologica ◽

10.1360/n092016-00249 ◽

2017 ◽

Vol 47 (2) ◽

pp. 170-175

Author(s):

Feng LI ◽

JinChao SHI ◽

WeiGuang YANG ◽

Bo YU ◽

DengYuan SONG ◽

...

Keyword(s):

Solar Cell ◽

Carrier Lifetime ◽

Minority Carrier ◽

Minority Carrier Lifetime ◽

Heterojunction Solar Cell ◽

Cell Production

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Enhancement of Minority Carrier Lifetime in Ultra-High Voltage 4H-SiC PiN Diodes by Carbon-Film Annealing

Materials Science Forum ◽

10.4028/www.scientific.net/msf.1014.137 ◽

2020 ◽

Vol 1014 ◽

pp. 137-143

Author(s):

Wen Ting Zhang ◽

Yun Lai An ◽

Yi Ying Zha ◽

Ling Sang ◽

Jing Hua Xia ◽

...

Keyword(s):

High Temperature ◽

Carrier Lifetime ◽

Minority Carrier ◽

Carbon Film ◽

Minority Carrier Lifetime ◽

Pin Diodes ◽

High Temperature Anneal ◽

Thin Carbon ◽

Drift Layer ◽

Lifetime Enhancement

A novel process is developed for minority carrier lifetime enhancement in ultra-high 4H-SiC PiN diodes. It comprises two separate processes. Firstly, the ultra-thick epitaxial grown drift layer (200μm) covered with a protective thin carbon film is subject to a 1500°C high-temperature anneal process in Ar atmosphere for 2 hours. Secondly, a surface passivation process is adopted to reduce the surface recombination rate. μ-PCD tests show that after high-temperature anneal, the thick drift layer shows a minority carrier lifetime increase to about 1.6 μs. PiN diodes based on the novel process are fabricated and their electric characteristics are measured. Results show a low specific on-resistance of 16.3 mΩ·cm2 at 25°C and 14 mΩ·cm2 at 125 °C. Compared with simulation results, it is shown that its effective minority carrier lifetime increase to about 5μs .Our study demonstrates that the developed novel process is effective in minority carrier lifetime enhancement in ultra-voltage 4H-SiC PiN diodes.

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