Enhancing Breakdown Voltage of a Ga2O3 Schottky Barrier Diode with Small-Angle Beveled and High-k Oxide Field Plate

To increase their breakdown voltage, Ga2O3 Schottky barrier diodes (SBDs) with a beveled field plate were designed based on TCAD platform simulations. The small-angle beveled field plate can effectively alleviate the electric field concentration effect. The breakdown voltage of Ga2O3 SBDs can reach 1217 V with the SiO2 dielectric and a small-angle (1°) beveled field plate. However, the breakdown mechanism is the early breakdown of the dielectric layer. TO further increase the breakdown voltage, the replacement of SiO2 with a high-k dielectric (Al2O3 and HfO2) can transfer the breakdown location into the Ga2O3 drift layer. By combining the beveled small-angle design and the high-k dielectric, the device demonstrates a Baliga’s figure of merit of 2.94 GW/cm2 and breakdown voltage of 3108V.

A Charge Balanced Vertical Power MOSFET With Record High Balliga’s Figure of Merit: Design and Investigation

In this work, we design and simulate a high-performance vertical power MOSFET with a charge balanced drift layer, which modulates the RON-BV relation from super quadratic to linear. The proposed device is designed with a super junction drift layer which modulates the RON-BV relation from super quadratic to linear. The proposed device has the source and channel regions isolated from the super junction drift layer. This results in a significant improvement in the performance of the proposed device in comparison to the other conventional devices, in terms of Balliga’s figure of merit. A 2D TCAD simulation study reveals that the proposed device with an epitaxial layer thickness of 50μm shows an ON resistance of 3.84mΩ.cm2 for a break down voltage of 833V, which is the lowest among the resistances reported in the previous literature at this breakdown voltage. Further, the study of charge imbalances and the capacitance analyses including the calculation of gate charge has also been done. The values of Balliga’s figure of merit (FOM) calculated for all the drift thicknesses of the proposed structures are significantly outperforming the conventional super junction structures reported so far.

Enhancement of Minority Carrier Lifetime in Ultra-High Voltage 4H-SiC PiN Diodes by Carbon-Film Annealing

A novel process is developed for minority carrier lifetime enhancement in ultra-high 4H-SiC PiN diodes. It comprises two separate processes. Firstly, the ultra-thick epitaxial grown drift layer (200μm) covered with a protective thin carbon film is subject to a 1500°C high-temperature anneal process in Ar atmosphere for 2 hours. Secondly, a surface passivation process is adopted to reduce the surface recombination rate. μ-PCD tests show that after high-temperature anneal, the thick drift layer shows a minority carrier lifetime increase to about 1.6 μs. PiN diodes based on the novel process are fabricated and their electric characteristics are measured. Results show a low specific on-resistance of 16.3 mΩ·cm2 at 25°C and 14 mΩ·cm2 at 125 °C. Compared with simulation results, it is shown that its effective minority carrier lifetime increase to about 5μs .Our study demonstrates that the developed novel process is effective in minority carrier lifetime enhancement in ultra-voltage 4H-SiC PiN diodes.