Stepwise Transformation of Algorithms
into Array Processor Architectures
by the DECOMP

A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

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Efficient FPGA-Based Architecture of the Overlap-Add Method for Short-Time Fourier Analysis/Synthesis

Electronics ◽

10.3390/electronics8121533 ◽

2019 ◽

Vol 8 (12) ◽

pp. 1533 ◽

Cited By ~ 2

Author(s):

Mohammed Bahoura

Keyword(s):

Fourier Analysis ◽

Field Programmable Gate Array ◽

Original Signal ◽

Programming Tool ◽

Objective Metrics ◽

Field Programmable ◽

Signal Processing Algorithms ◽

Processing Algorithms ◽

High Level ◽

Short Time

This paper proposes a simple and efficient FPGA-based architecture of the overlapping/windowing and overlap-add methods for real-time FFT/IFFT-based signal processing algorithms. The analyzed signal is divided into short-time overlapping frames that are windowed before applying Fourier analysis/synthesis. Then, the original signal is reconstructed from the windowed (modified) frames using the overlap-add (OLA) technique. The proposed architecture was implemented on Field Programmable Gate Array (FPGA) using a high-level programming tool in MATLAB/SIMULINK environment. Its performance was evaluated on artificial and actual signals using objective metrics.

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FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard

Journal of Communications Technology Electronics and Computer Science ◽

10.22385/jctecs.v1i0.2 ◽

2015 ◽

Vol 1 ◽

pp. 1 ◽

Cited By ~ 1

Author(s):

Muhammad Ibn Ibrahimy

Keyword(s):

Implementation Process ◽

Digital Signal ◽

Multimedia Data ◽

Floating Point ◽

Point Multiplication ◽

Quartus Ii ◽

Field Programmable ◽

Hardware Description ◽

High Level ◽

Complexity Of Algorithm

This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.

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