scholarly journals Low-Cost Allocator Implementations for Networks-on-Chip Routers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10
Author(s):  
Min Zhang ◽  
Chiu-Sing Choy
Keyword(s):  
Low Cost ◽  
Virtual Channel ◽  
Careful Study ◽  
Network Simulator ◽  
Networks On Chip ◽  
Look Ahead ◽  
Generic Architecture ◽  
On Chip ◽  
The Look ◽  
The Impact

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

scholarly journals Avaliação de Desempenho de Redes-em-Chip Sem Fio Single-Hop com NAS Parallel Benchmarks

2013 ◽  
Author(s):  
Amanda Maria P. Amorim ◽  
Henrique C. Freitas
Keyword(s):  
Wireless Networks ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Network Simulator ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

Em arquiteturas tradicionais de redes-em-chip, há influência do fio que pode reduzir a escalabilidade, rendimento e eficiência. Redes-em-chip sem fio (Wireless Networks-on-Chip WiNoCs) são alternativas para fornecer comunicação entre núcleos de processadores many-core com alta largura de banda e baixo consumo de energia. Em aplicações paralelas há comunicações entre vários núcleos demandando um projeto de rede-em-chip eficiente. Portanto, o objetivo deste trabalho é projetar e avaliar uma arquitetura WiNoC single-hop usando cargas de trabalho paralelas. A metodologia é baseada em simulações através do simulador de rede NS-2 (Network Simulator) e aplicações do NAS Parallel Benchmarks (NPB). A arquitetura WiNoC é baseada na topologia mesh 2-D com tecnologia de rádio UWB (Ultra Wide Band). A transmissão entre núcleos é avaliada com base nas comunicações unicast (1:1 e N: 1) e broadcast (1: N e N: N). A arquitetura WiNoC Single-hop tem alto desempenho nas comunicação broadcast, alcançando no máximo 2,21 % de perda de pacotes. Nas comunicações unicast, a WiNoC single-hop tem alto desempenho atingindo no máximo 0,02 % de perda de pacotes e 0,2 ms de latência. A maior taxa de perda de pacotes e latência ocorrem nas comunicações N:1, devido a concorrência dos pacotes pelo nó destino. A WiNoC Single-hop alcançou até 63,12 J de consumo de energia. É possível concluir que a arquitetura WiNoC Single-hop apresenta alto desempenho, mas precisa de melhorias para reduzir o consumo de energia aumentando a sua eficiência.

Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy

2020 ◽  
Vol 29 (16) ◽  
pp. 2050263
Author(s):  
Anirban Bhattacharjee ◽  
Chandan Bandyopadhyay ◽  
Bappaditya Mondal ◽  
Hafizur Rahaman
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Physical Realization ◽  
Emerging Trends ◽  
Look Ahead ◽  
Wide Range ◽  
Clustering Approach ◽  
On Chip ◽  
The Impact

In the last couple of years, quantum computing has come out as emerging trends of computation not only due to its immense popularity but also for its commitment towards physical realization of quantum circuit in on-chip units. At the same time, the process of physical realization has faced several design constraints and one such problem is nearest neighbor (NN) enforcement which demands all the operating qubits to be placed adjacent in the implementable circuit. Though SWAP gate embedment can transform a design into NN architecture, it still creates overhead in the design. So, designing algorithms to restrict the use of SWAPs bears high importance. Considering this fact, in this work, we are proposing a heuristic-based improved qubit placement strategy for efficient implementation of NN circuit. Two different design policies are being developed here. In the first scheme, a global reordering technique based on clustering approach is shown. In the second scheme, a local reordering technique based on look-ahead policy is developed. This look-ahead strategy considers the impact over the gates in the circuit and thereby estimates the effect using a cost metric to decide the suitable option for SWAP implementation. Furthermore, the joint use of both the ordering schemes also has been explored here. To ascertain the correctness of our design algorithms, we have tested them over a wide range of benchmarks and the obtained results are compared with some state-of-the-art design approaches. From this comparison, we have witnessed a considerable reduction on SWAP cost in our design scheme against the reported works’ results.

scholarly journals Low cost fault-tolerant routing algorithm for Networks-on-Chip

2015 ◽  
Vol 39 (6) ◽  
pp. 358-372 ◽  
Author(s):  
Junxiu Liu ◽  
Jim Harkin ◽  
Yuhua Li ◽  
Liam Maguire
Keyword(s):  
Fault Tolerant ◽  
Low Cost ◽  
Routing Algorithm ◽  
Networks On Chip ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document