Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy

2020 ◽  
Vol 29 (16) ◽  
pp. 2050263
Author(s):  
Anirban Bhattacharjee ◽  
Chandan Bandyopadhyay ◽  
Bappaditya Mondal ◽  
Hafizur Rahaman
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Physical Realization ◽  
Emerging Trends ◽  
Look Ahead ◽  
Wide Range ◽  
Clustering Approach ◽  
On Chip ◽  
The Impact

In the last couple of years, quantum computing has come out as emerging trends of computation not only due to its immense popularity but also for its commitment towards physical realization of quantum circuit in on-chip units. At the same time, the process of physical realization has faced several design constraints and one such problem is nearest neighbor (NN) enforcement which demands all the operating qubits to be placed adjacent in the implementable circuit. Though SWAP gate embedment can transform a design into NN architecture, it still creates overhead in the design. So, designing algorithms to restrict the use of SWAPs bears high importance. Considering this fact, in this work, we are proposing a heuristic-based improved qubit placement strategy for efficient implementation of NN circuit. Two different design policies are being developed here. In the first scheme, a global reordering technique based on clustering approach is shown. In the second scheme, a local reordering technique based on look-ahead policy is developed. This look-ahead strategy considers the impact over the gates in the circuit and thereby estimates the effect using a cost metric to decide the suitable option for SWAP implementation. Furthermore, the joint use of both the ordering schemes also has been explored here. To ascertain the correctness of our design algorithms, we have tested them over a wide range of benchmarks and the obtained results are compared with some state-of-the-art design approaches. From this comparison, we have witnessed a considerable reduction on SWAP cost in our design scheme against the reported works’ results.

scholarly journals An Innovative Genetic Algorithm for the Quantum Circuit Compilation Problem

2019 ◽  
Vol 33 ◽  
pp. 7707-7714
Author(s):  
Riccardo Rasconi ◽  
Angelo Oddi
Keyword(s):  
Genetic Algorithm ◽  
Nearest Neighbor ◽  
Quantum Algorithms ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Heuristic Function ◽  
Circuit Realization ◽  
Benchmark Instances ◽  
Technological Limitations ◽  
Selection Of

Quantum Computing represents the next big step towards speed boost in computation, which promises major breakthroughs in several disciplines including Artificial Intelligence. This paper investigates the performance of a genetic algorithm to optimize the realization (compilation) of nearest-neighbor compliant quantum circuits. Currrent technological limitations (e.g., decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized, and therefore the makespanminimization problem of compiling quantum algorithms on present or future quantum machines is dragging increasing attention in the AI community. In our genetic algorithm, a solution is built utilizing a novel chromosome encoding where each gene controls the iterative selection of a quantum gate to be inserted in the solution, over a lexicographic double-key ranking returned by a heuristic function recently published in the literature.Our algorithm has been tested on a set of quantum circuit benchmark instances of increasing sizes available from the recent literature. We demonstrate that our genetic approach obtains very encouraging results that outperform the solutions obtained in previous research against the same benchmark, succeeding in significantly improving the makespan values for a great number of instances.

Analyzing Heuristic-based Randomized Search Strategies for the Quantum Circuit Compilation Problem

2020 ◽  
Vol 174 (3-4) ◽  
pp. 259-281
Author(s):  
Angelo Oddi ◽  
Riccardo Rasconi
Keyword(s):  
Quantum Computing ◽  
Nearest Neighbor ◽  
Quantum Algorithm ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Ranking Functions ◽  
Solution Quality ◽  
Circuit Realization ◽  
Definition Of

In this work we investigate the performance of greedy randomised search (GRS) techniques to the problem of compiling quantum circuits to emerging quantum hardware. Quantum computing (QC) represents the next big step towards power consumption minimisation and CPU speed boost in the future of computing machines. Quantum computing uses quantum gates that manipulate multi-valued bits (qubits). A quantum circuit is composed of a number of qubits and a series of quantum gates that operate on those qubits, and whose execution realises a specific quantum algorithm. Current quantum computing technologies limit the qubit interaction distance allowing the execution of gates between adjacent qubits only. This has opened the way to the exploration of possible techniques aimed at guaranteeing nearest-neighbor (NN) compliance in any quantum circuit through the addition of a number of so-called swap gates between adjacent qubits. In addition, technological limitations (decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized. One core contribution of the paper is the definition of two lexicographic ranking functions for quantum gate selection, using two keys: one key acts as a global closure metric to minimise the solution makespan; the second one is a local metric, which favours the mutual approach of the closest qstates pairs. We present a GRS procedure that synthesises NN-compliant quantum circuits realizations, starting from a set of benchmark instances of different size belonging to the Quantum Approximate Optimization Algorithm (QAOA) class tailored for the MaxCut problem. We propose a comparison between the presented meta-heuristics and the approaches used in the recent literature against the same benchmarks, both from the CPU efficiency and from the solution quality standpoint. In particular, we compare our approach against a reference benchmark initially proposed and subsequently expanded in [1] by considering: (i) variable qubit state initialisation and (ii) crosstalk constraints that further restrict parallel gate execution.

An efficient conversion of quantum circuits to a linear nearest neighbor architecture

2011 ◽  
Vol 11 (1&2) ◽  
pp. 142-166
Author(s):  
Yuichi Hirata ◽  
Masaki Nakanishi ◽  
Shigeru Yamashita ◽  
Yasuhiko Nakashima
Keyword(s):  
Quantum Computation ◽  
Time Complexity ◽  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Bits ◽  
Efficient Conversion ◽  
Conversion Method ◽  
Additional Circuitry

Several promising implementations of quantum computation rely on a Linear Nearest Neighbor (LNN) architecture, which arranges quantum bits on a line, and allows neighbor interactions only. Therefore, several specific circuits have been designed on an LNN architecture. However, a general and efficient conversion method for an arbitrary circuit has not been established. Therefore, this paper gives an efficient conversion technique to convert quantum circuits to an LNN architecture. When a quantum circuit is converted to an LNN architecture, the objective is to reduce the size of the additional circuit added by the conversion and the time complexity of the conversion. The proposed method requires less additional circuitry and time complexity compared with naive techniques. To develop the method, we introduce two key theorems that may be interesting on their own. In addition, the proposed method also achieves less overhead than some known circuits designed from scratch on an LNN architecture.

scholarly journals ON THE GAP OF HAMILTONIANS FOR THE ADIABATIC SIMULATION OF QUANTUM CIRCUITS

2013 ◽  
Vol 11 (07) ◽  
pp. 1350063 ◽  
Author(s):  
ANAND GANTI ◽  
ROLANDO SOMMA
Keyword(s):  
Upper Bound ◽  
Spectral Gap ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Search Problem ◽  
Adiabatic Evolution ◽  
Unstructured Search ◽  
Time Quantum ◽  
The Cost ◽  
The Impact

The time or cost of simulating a quantum circuit by adiabatic evolution is determined by the spectral gap of the Hamiltonians involved in the simulation. In "standard" constructions based on Feynman's Hamiltonian, such a gap decreases polynomially with the number of gates in the circuit, L. Because a larger gap implies a smaller cost, we study the limits of spectral gap amplification in this context. We show that, under some assumptions on the ground states and the cost of evolving with the Hamiltonians (which apply to the standard constructions), an upper bound on the gap of the order 1/L follows. In addition, if the Hamiltonians satisfy a frustration-free property, the upper bound is of the order 1/L2. Our proofs use recent results on adiabatic state transformations, spectral gap amplification, and the simulation of continuous-time quantum query algorithms. They also consider a reduction from the unstructured search problem, whose lower bound in the oracle cost translates into the upper bounds in the gaps. The impact of our results is that improving the gap beyond that of standard constructions (i.e. 1/L2), if possible, is challenging.

scholarly journals Low-Cost Allocator Implementations for Networks-on-Chip Routers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10
Author(s):  
Min Zhang ◽  
Chiu-Sing Choy
Keyword(s):  
Low Cost ◽  
Virtual Channel ◽  
Careful Study ◽  
Network Simulator ◽  
Networks On Chip ◽  
Look Ahead ◽  
Generic Architecture ◽  
On Chip ◽  
The Look ◽  
The Impact

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits

2016 ◽  
Author(s):  
Robert Wille ◽  
Oliver Keszocze ◽  
Marcel Walter ◽  
Patrick Rohrs ◽  
Anupam Chattopadhyay ◽  
...  
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuits ◽  
Look Ahead

scholarly journals A Transformation-Based Quantum Physical Synthesis Approach for Nearest-Neighbor Architectures

2021 ◽  
Vol 3 (3) ◽  
pp. 435-443
Author(s):  
Golriz Hoseinimanesh ◽  
Naser Mohammadzadeh
Keyword(s):  
Simulated Annealing ◽  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Transformation Rule ◽  
Transformation Rules ◽  
Target Architecture ◽  
Physical Synthesis ◽  
Synthesis Approach ◽  
Mapping Information

The physical synthesis concept for quantum circuits, the interaction between synthesis and physical design processes, was first introduced in our previous work. This concept inspires us to propose some techniques that can minimize the number of extra inserted SWAP operations required to run a circuit on a nearest-neighbor architecture. Minimizing the number of SWAP operations potentially decreases the latency and error probability of a quantum circuit. Focusing on this concept, we present a physical synthesis technique based on transformation rules to decrease the number of SWAP operations in nearest-neighbor architectures. After the qubits of a circuit are mapped onto the physical qubits provided by the target architecture, our procedure is fed by this mapping information. Our method uses the obtained placement and scheduling information to apply some transformation rules to the original netlist to decrease the number of extra SWAP gates required for running the circuit on the architecture. We follow two policies in applying a transformation rule, greedy and simulated-annealing-based policies. Simulation results show that the proposed technique decreases the average number of extra SWAP operations by about 20.6% and 24.1% based on greedy and simulated-annealing-based policies, respectively, compared with the best in the literature.

A method for synthesis and optimization for linear nearest neighbor quantum circuits by parallel processing

2018 ◽  
Vol 18 (13&14) ◽  
pp. 1095-1114
Author(s):  
Zongyuan Zhang ◽  
Zhijin Guan ◽  
Hong Zhang ◽  
Haiying Ma ◽  
Weiping Ding
Keyword(s):  
Parallel Processing ◽  
Large Scale ◽  
Nearest Neighbor ◽  
Matrix Multiplication ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Cost ◽  
The Matrix ◽  
Speed Up ◽  
Serial Algorithm

In order to realize the linear nearest neighbor{(LNN)} of the quantum circuits and reduce the quantum cost of linear reversible quantum circuits, a method for synthesizing and optimizing linear reversible quantum circuits based on matrix multiplication of the structure of the quantum circuit is proposed. This method shows the matrix representation of linear quantum circuits by multiplying matrices of different parts of the whole circuit. The LNN realization by adding the SWAP gates is proposed and the equivalence of two ways of adding the SWAP gates is proved. The elimination rules of the SWAP gates between two overlapped adjacent quantum gates in different cases are proposed, which reduce the quantum cost of quantum circuits after realizing the LNN architecture. We propose an algorithm based on parallel processing in order to effectively reduce the time consumption for large-scale quantum circuits. Experiments show that the quantum cost can be improved by 34.31\% on average and the speed-up ratio of the GPU-based algorithm can reach 4 times compared with the CPU-based algorithm. The average time optimization ratio of the benchmark large-scale circuits in RevLib processed by the parallel algorithm is {95.57\%} comparing with the serial algorithm.

A method of mapping and nearest neighbor optimization for 2-D quantum circuits

2020 ◽  
Vol 20 (3&4) ◽  
pp. 194-212
Author(s):  
Yuxin Zhang ◽  
Zhijin Guan ◽  
Longyong Ji ◽  
Qin Fang Luan ◽  
Yizhen Wang
Keyword(s):  
Quantum Computation ◽  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Mapping Method ◽  
Quantum Circuits ◽  
Grid Structure ◽  
Quantum Bits ◽  
Physical Constraints ◽  
Swap Gate ◽  
Qubit Gate

In some practical quantum physical architectures, the qubits need to be distributed on 2-dimensional (2-D) grid structure to implement quantum computation. In order to map an 1-dimensional (1-D) quantum circuit into a 2-D grid structure and satisfy the nearest neighbor constraint of qubit interaction in the grid structure, a mapping method from 1-D quantum circuit to 2-D grid structure is proposed in this paper. This method firstly determines the order of placing qubits, and then presents the layout strategy of qubits in 2-D grid. We also proposed an algorithm for establishing interaction paths between non-adjacent qubits in 2-D grid structure, which can satisfy the physical constraints of the interaction of quantum bits in the grid in the process of mapping an 1-D quantum circuit to a 2-D grid structure. For some benchmark circuits, after using the method of this paper to place qubits, it is possible to make every 2-qubit gate in the circuit have a nearest neighbor, so that there is no need to use SWAP gate to establish channel routing. Compared with the latest available methods, the average optimization rate is 82.38%.

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