Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.

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Single Trace Side Channel Analysis on NTRU Implementation

Applied Sciences ◽

10.3390/app8112014 ◽

2018 ◽

Vol 8 (11) ◽

pp. 2014 ◽

Cited By ~ 1

Author(s):

Soojung An ◽

Suhri Kim ◽

Sunghyun Jin ◽

HanBit Kim ◽

HeeSeok Kim

Keyword(s):

Power Consumption ◽

Quantum Computer ◽

Side Channel ◽

Side Channel Attacks ◽

Side Channel Analysis ◽

Channel Analysis ◽

Post Quantum Cryptography ◽

Single Trace ◽

Secure Implementation ◽

Single Power

As researches on the quantum computer have progressed immensely, interests in post-quantum cryptography have greatly increased. NTRU is one of the well-known algorithms due to its practical key sizes and fast performance along with the resistance against the quantum adversary. Although NTRU has withstood various algebraic attacks, its side-channel resistance must also be considered for secure implementation. In this paper, we proposed the first single trace attack on NTRU. Previous side-channel attacks on NTRU used numerous power traces, which increase the attack complexity and limit the target algorithm. There are two versions of NTRU implementation published in succession. We demonstrated our attack on both implementations using a single power consumption trace obtained in the decryption phase. Furthermore, we propose a countermeasure to prevent the proposed attacks. Our countermeasure does not degrade in terms of performance.

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Power Side Channel Analysis and Anomaly Detection of Modular Exponentiation Method in Digital Signature Algorithm Based Fpga

ITM Web of Conferences ◽

10.1051/itmconf/20182201041 ◽

2018 ◽

Vol 22 ◽

pp. 01041

Author(s):

Burcu Sönmez ◽

Ahmet Bedri Özer

Keyword(s):

Anomaly Detection ◽

Power Consumption ◽

Digital Signature ◽

Detection Method ◽

Chinese Remainder Theorem ◽

Side Channel ◽

Modular Exponentiation ◽

Side Channel Analysis ◽

Digital Signature Algorithm ◽

Channel Analysis

In this study, digital signature application was performed on FPGA with classical RSA and Chinese Remainder Theorem (CRT). The power consumption of the system was observed when the digital signature process was performed on the FPGA. In order to distinguish the modular exponentiation methods as the classical RSA and the Chinese Remainder Theorem (CRT), the anomaly detection method was applied to the digital signature application using the power side channel analysis of the system. According to the obtained result, it is proved that information about the structure of the algorithm executing in the system can be obtained by using the power information consumed by a cryptographic device.

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