scholarly journals Development of Multiobjective High-Level Synthesis for FPGAs

2020 ◽  
Vol 2020 ◽  
pp. 1-25
Author(s):  
Darian Reyes Fernandez de Bulnes ◽  
Yazmin Maldonado ◽  
Leonardo Trujillo
Keyword(s):  
Design Space Exploration ◽  
Optimization Methods ◽  
Digital Circuit ◽  
High Level Synthesis ◽  
Objective Functions ◽  
Trade Offs ◽  
Field Programmable ◽  
Digital Circuit Designs ◽  
And Performance ◽  
High Level

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

scholarly journals High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1494 ◽  
Author(s):  
Abelardo Baez ◽  
Himar Fabelo ◽  
Samuel Ortega ◽  
Giordana Florimbi ◽  
Emanuele Torti ◽  
...  
Keyword(s):  
Brain Cancer ◽  
Research Field ◽  
Hyperspectral Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Code Refactoring ◽  
Field Programmable ◽  
And Performance ◽  
High Level

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

scholarly journals High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth Memory

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1275
Author(s):  
Changdao Du ◽  
Yoshiki Yamaguchi
Keyword(s):  
Programming Languages ◽  
High Performance ◽  
Design Space Exploration ◽  
Scale Up ◽  
High Level Synthesis ◽  
Stencil Computations ◽  
Temporal Domain ◽  
High Bandwidth ◽  
Promising Solution ◽  
High Level

Due to performance and energy requirements, FPGA-based accelerators have become a promising solution for high-performance computations. Meanwhile, with the help of high-level synthesis (HLS) compilers, FPGA can be programmed using common programming languages such as C, C++, or OpenCL, thereby improving design efficiency and portability. Stencil computations are significant kernels in various scientific applications. In this paper, we introduce an architecture design for implementing stencil kernels on state-of-the-art FPGA with high bandwidth memory (HBM). Traditional FPGAs are usually equipped with external memory, e.g., DDR3 or DDR4, which limits the design space exploration in the spatial domain of stencil kernels. Therefore, many previous studies mainly relied on exploiting parallelism in the temporal domain to eliminate the bandwidth limitations. In our approach, we scale-up the design performance by considering both the spatial and temporal parallelism of the stencil kernel equally. We also discuss the design portability among different HLS compilers. We use typical stencil kernels to evaluate our design on a Xilinx U280 FPGA board and compare the results with other existing studies. By adopting our method, developers can take broad parallelization strategies based on specific FPGA resources to improve performance.

scholarly journals A rapid design space exploration approach for multi-objective optimization of DSP filter designs

2021 ◽  
Author(s):  
Aakriti Tarun Sharma
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Systems Design ◽  
Design Solution ◽  
Multi Objective Optimization ◽  
Multi Objective ◽  
Time Period ◽  
And Performance ◽  
High Level

The process of converting a behavioral specification of an application to its equivalent system architecture is referred to as High Level-Synthesis (HLS). A crucial stage in embedded systems design involves finding the trade off between resource utilization and performance. An exhaustive search would yield the required results, but would take a huge amount of time to arrive at the solution even for smaller designs. This would result in a high time complexity. We employ the use of Design Space Exploration (DSE) in order to reduce the complexity of the design space and to reach the desired results in less time. In reality, there are multiple constraints defined by the user that need to be satisfied simultaneously. Thus, the nature of the task at hand is referred to as Multi-Objective Optimization. In this thesis, the design process of DSP benchmarks was analyzed based on user defined constraints such as power and execution time. The analyzed outcome was compared with the existing approaches in DSE and an optimal design solution was derived in a shorter time period.

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis

2020 ◽  
Vol 39 (11) ◽  
pp. 3736-3747
Author(s):  
Lorenzo Ferretti ◽  
Jihye Kwon ◽  
Giovanni Ansaloni ◽  
Giuseppe Di Guglielmo ◽  
Luca P. Carloni ◽  
...  
Keyword(s):  
Prior Knowledge ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
High Level ◽  
Effective Design
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