scholarly journals Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

2020 ◽  
Vol 9 (1) ◽  
pp. 396-402
Author(s):  
S. A. Z. Murad ◽  
A. Azizan ◽  
A. F. Hasan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Return Loss ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wireless Sensor ◽  
Total Power ◽  
Ultra Low Power ◽  
Noise Amplifier

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

A 0.3 mW 2.4 GHZ LOW POWER LOW NOISE AMPLIFIER USING FORWARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR ARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR NETWORK

2015 ◽  
Vol 78 (1) ◽  
Author(s):  
Anishaziela Azizan ◽  
Sohiful Anuar Zainol Murad
Keyword(s):  
Wireless Sensor Network ◽  
Power Consumption ◽  
Low Power ◽  
Return Loss ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wireless Sensor ◽  
Noise Amplifier ◽  
Forward Body Bias ◽  
Body Bias

This paper presents a 0.3 mW 2.4 GHz low-power low-noise amplifier (LNA) using a forward-body bias technique for a wireless sensor network. The proposed LNA is implemented using CMOS 0.13-µm Silterra technology. The forward-body bias technique with a cascode configuration has been adopted in order to obtain low power consumption. A low supply voltage of 0.5 V is used to optimize the trade-offs between the LNA performances. The post-layout simulation results indicate that a power consumption of 0.3 mW is achieved. The simulated input return loss (S11) is less than -17.71 dB while the output return loss (S22) is below -14.83 dB. Moreover, the gain (S21) of 9.86 dB, the noise figure (NF) of 5.11 dB and the input-referred third-order intercept point (IIP3) of -7.5 dBm at 2.4 GHz is obtained with the calculated figure of merit (FOM) of 4.64 (1/mW).

Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network

2019 ◽  
pp. 1-6
Author(s):  
Sohiful Anuar Zainol Murad ◽  
Anishaziela Azizan ◽  
Rohana Sapawi ◽  
Tun Zainal Azni Zulkifli
Keyword(s):  
Wireless Sensor Network ◽  
Low Power ◽  
Sensor Network ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wireless Sensor ◽  
Ultra Low Power ◽  
Noise Amplifier

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

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