3D Technology Computer-Aided Design-Based Optimization of Channel Radius Considering Line Edge Roughness on Gate-All-Around Nanowire FET

2017 ◽  
Vol 17 (5) ◽  
pp. 3060-3064 ◽  
Author(s):  
Dokyun Son ◽  
Kyul Ko ◽  
Myounggon Kang ◽  
Hyungcheol Shin
Keyword(s):  
Computer Aided Design ◽  
Line Edge Roughness ◽  
3D Technology ◽  
Channel Radius ◽  
Edge Roughness ◽  
Computer Aided ◽  
Aided Design

Study on Application of CAD Used in Visual Advertising Design

2014 ◽  
Vol 571-572 ◽  
pp. 768-771
Author(s):  
Jun Liu
Keyword(s):  
Computer Aided Design ◽  
Television Advertising ◽  
Paper Study ◽  
Application Technology ◽  
Visual Effects ◽  
3D Technology ◽  
Wide Range ◽  
Computer Aided ◽  
Visual Impact ◽  
Aided Design

The 3D technology currently has in various engineering fields have a wide range of applications, all the 3D visual effects technology can bring us visual impact, the use of 3D technology produced by the television advertising more easily accepted by the audience, this paper study on the 3D computer-aided design advertising design application technology.

Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 142-146
Author(s):  
Liang Dai ◽  
Wei-Feng Lü
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Line Edge Roughness ◽  
Metal Gate ◽  
Edge Roughness ◽  
Simulation Results ◽  
Dual Metal ◽  
Aided Design ◽  
First Time

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

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