Two Simulation Tools for Testing ATM Resource Allocation Strategies

SIMULATION ◽  
1997 ◽  
Vol 68 (1) ◽  
pp. 9-22
Author(s):  
Raffaele Bolla ◽  
Ahmad Dalal'Ah ◽  
Franco Davoli ◽  
Mario Marchese

Two event-driven simulation tools aimed at testing access control and routing mechanisms in an Asynchronous Transfer Mode (ATM) environment are presented. The first one is dedicated to the behavioural description of an ATM Virtual Circuit (VC) switch. The purpose is to test resource allocation and Call Admission Control (CAC) strategies, so only the relevant events for this objective are considered and some important functions (e.g., the switching element) for a complete description of an ATM switch are not explicitly modeled. The second simulator has been designed to test routing strategies for an ATM network. In such a case, a higher level of abstraction than in the previous one is necessary and, again, only the meaningful events to the aim are taken into account. Some resource allocation, CAC, and routing schemes are also reported, along with the description of the simulation tools. Several simulation results are discussed, in order to assess their performance.

Author(s):  
Hans Hellendoorn ◽  
Rudolf Seising

We describe applications of fuzzy logic in the area of broadband telecommunication networks. Call Admission Control (CAC) and Usage Parameter Control (UPC) play an important role in the traffic management of ATM networks (Asynchronous Transfer Mode). We present "fuzzy solutions" for this control tasks and we show their success by presenting simulation results and heuristic valuations.


Author(s):  
Vishal Chandra , Et. al.

In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.


IEE Review ◽  
1991 ◽  
Vol 37 (10) ◽  
pp. 357
Author(s):  
C.J. Hughes ◽  
A. (Gill) Waters

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