Single-Chip Multiprocessing For Consumer Electronics

2003 ◽  
Author(s):  
Paul Stravers ◽  
Jan Hoogerbugge
Keyword(s):  
Consumer Electronics ◽  
Single Chip

Smart-TV – ein interdisziplinärer Überblick

2013 ◽  
Vol 10 (3) ◽  
pp. 26-37
Author(s):  
Patrick Godefroid ◽  
Tobias Keber ◽  
Boris A. Kühnle ◽  
Oliver Zöllner
Keyword(s):  
Consumer Electronics ◽  
Smart Tv

Smart-TVs mit immer eindrucksvolleren Fähigkeiten sind der Trend im Bereich der Consumer Electronics. Die intelligenten Geräte sind nicht nur eine technische Neuerung, sondern sie stellen traditionelle Konzepte in Wirtschaft, Recht, Politik und Gesellschaft vor große Herausforderungen. Die bisweilen auch als „Hybrid-TV“ bezeichneten Gerate stehen für eine neue Dimension der Konvergenz und rücken als Forschungsgegenstand in den Fokus ganz unterschiedlicher medienwissenschaftlicher Disziplinen. Technisch muss man sich zunächst einmal klarmachen, wie die Verschmelzung von Fernseh- und Online- Welt tatsächlich funktioniert und welche Begrifflichkeiten die neue Fernsehwelt hervorgebracht hat. In wirtschaftlicher Hinsicht stellt sich dann unter anderem die Frage, wie weit Charakteristika der Internet-Ökonomie bei einem Verknüpfen von Internet und Fernsehen Implikationen für die Erlös- und Refinanzierungsmodelle des TV haben. Ob die noch immer rundfunkzentrierten Vorgaben des Medienrechts die mit Smart-TV einhergehenden Fragen tatsachlich noch sachgerecht adressieren, ist fraglich, was einen Blick auf die medienpolitische Entwicklung erforderlich macht. Schließlich besteht Erörterungsbedarf dahingehend, wie sich der stärkere Grad der Individualisierung von Inhalten und die damit verbundene Zersplitterung der Rezeptionswirkung auf die Gesellschaft auswirken.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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