Session 1(b): Basic Techniques—Electronics: A Review of Postal Engineering Logic Units

1969 ◽  
Vol 184 (8) ◽  
pp. 41-51
Author(s):  
H. Goodison
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Design Method ◽  
Circuit Board ◽  
Actual Performance ◽  
Printed Circuit ◽  
Large Scale Integration ◽  
Current Assessment ◽  
Standard Set ◽  
Scale Integration

The paper describes why control elements using discrete components mounted on a printed circuit board were chosen for postal mechanization equipments. Basic design considerations are listed, and principles determining the choice of components stated. The decision to provide both ‘nor’ and ‘not-and’ elements is explained, and the reasons given why negative logic is used. With the use of B.S. symbols it is shown how logic diagrams can easily be converted to functional diagrams. A brief description of each logic unit in the standard set is given and the set of peripheral units listed. Mention is made of the design method and the emphasis placed on noise immunity. Constructional techniques and the use of an automatic tester are described. Current assessment of the actual performance of the units is given and future possibilities, including large-scale integration and M.O.S.T. devices, are discussed.

Two-Level Nonlinear Mixed Discrete-Continuous Optimization-Based Design: An Application to Printed Circuit Board Assemblies

1992 ◽  
Vol 114 (4) ◽  
pp. 425-435 ◽  
Author(s):  
S. Praharaj ◽  
S. Azarm
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Continuous Optimization ◽  
The Other ◽  
Circuit Board ◽  
Continuous Variables ◽  
Discrete Variables ◽  
Printed Circuit ◽  
Monotonicity Analysis ◽  
Optimization Based Design

In this paper, a new approach for optimization-based design of nonlinearly mixed discrete-continuous problems has been developed. The approach is based on a two-level decomposition strategy in which the entire domain of variables is partitioned into two levels, one involving the continuous variables and the other involving the discrete variables. Variables in one level are optimized for fixed values of the variable from the other level. A modified penalty function is formed, based on monotonicity analysis, to solve for the discrete variables, and a conventional optimization method is used to solve for the continuous variables. To improve the computational effectiveness of the approach, a constrained derivative relationship is also adopted. The performance of the entire algorithm is then demonstrated through an example involving a simplified model for printed circuit board assemblies. The objective in the example is to maximize assembly reliability by: (1) adding redundant components to the boards, and (2) optimally distributing allocated mass flow to the individual channels of the circuit boards. Number of variables in the example is then varied to investigate the effectiveness and potential of the approach for large-scale problems.

Two-Level Nonlinear Mixed Discrete-Continuous Optimization-Based Design: An Application to Printed Circuit Board Assemblies

1992 ◽  
Author(s):  
S. Praharaj ◽  
Shapour Azarm
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Continuous Optimization ◽  
The Other ◽  
Circuit Board ◽  
Continuous Variables ◽  
Discrete Variables ◽  
Printed Circuit ◽  
Monotonicity Analysis ◽  
Optimization Based Design

Abstract In this paper, a new approach for optimization-based design of non-linearly mixed discrete-continuous problems has been developed. The approach is based on a two-level decomposition strategy in which the entire domain of variables is partitioned into two levels, one involving the continuous variables and the other involving the discrete variables. Variables in one level are optimized for fixed values of the variable from the other level. A modified penalty function is formed, based on monotonicity analysis, to solve for the discrete variables, and a conventional optimization method was used to solve for the continuous variables. To improve the computational effectiveness of the approach, a constrained derivative relationship was also adopted. The performance of the entire algorithm is then demonstrated through an example involving printed circuit board assemblies. The objective in the example is to maximize assembly reliability by: (1) adding redundant components to the boards and (2) optimally distributing allocated mass flow to the individual channels of the circuit boards. Number of variables in the example is then varied to investigate the effectiveness and potential of the approach for large-scale problems.

Excimer Laser Drill for Multilayer Printed Circuit Boards: From Advanced Development to Factory Floor

MRS Bulletin ◽  
1989 ◽  
Vol 14 (12) ◽  
pp. 49-53 ◽  
Author(s):  
Friedrich Bachmann
Keyword(s):  
Excimer Laser ◽  
High Speed ◽  
Large Scale ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Multichip Module ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Delay Times

A novel excimer laser process has been developed for generating cylindrical via holes with an aspect ratio of about one. The fabrication process is being successfully run on a production line for a highly miniaturized printed circuit board used for the multichip module in the new Siemens 7500 H 90 mainframe computer. The process is outstanding in terms of reliability and reproducibility. To the best of our knowledge, this is the first that that excimer lasers have been put into large-scale use in an industrial environment.Since signal delay times for chips have decreased much more rapidly than delay times for packaging, the computing speed of high-speed computers is restricted by the packaging techniques used. Therefore, further development of packaging technology became a prime objective for those developing high-performance computers. Packaging delay times had to be reduced drastically to keep up with increasingly shorter chip delay times. This, in effect, meant that a greater packaging density had to be implemented.A novel planar packaging technique has lead to considerable progress in solving this problem. This technique has been described in detail elsewhere. A key component in this technology is a multichip module, which can take in each of 16 areas, either an LSI module with 320 leads or 9 MSI modules with 52 leads as “bare” ICs. This means that a micro-wiring printed circuit board of this kind can accomodate between 16 (LSI) and 144 (MSI) chips. This article describes how these printed circuit boards are manufactured.As the specifications (Table I) show, blind vias 80 μm in diameter at a pitch of 0.5 mm have to be made in a 16-layer printed circuit board. It is intended that these blind vias will provide the through-contact for neighboring layers. The excimer laser plays a major role in this process.

Designs of Eddy Current Sensor Probes Based on Multilayer Printed Circuit Board Technology

2012 ◽  
Vol 190-191 ◽  
pp. 801-805
Author(s):  
Kai Zhang ◽  
Xing Jian Dai ◽  
Xiao Zhang Zhang
Keyword(s):  
Eddy Current ◽  
Printed Circuit Board ◽  
Design Method ◽  
Design Principles ◽  
Circuit Board ◽  
Current Sensor ◽  
Current Field ◽  
Analysis And Design ◽  
Printed Circuit ◽  
Displacement Sensors

Probe characteristics are important for eddy current displacement sensors. Probes made by multilayer printed circuit board (PCB) are good at maintaining quality consistency and their axial length was short. As design principles for wired probes were not suitable for PCB probes, an analysis and design method for them was developed. In this paper, PCB probe characteristics were first analyzed with 3D eddy current field FEM software. The process was time-consuming. To increase analysis efficiency, a simplified 2D axial symmetry model was used to replace the 3D model. The analysis results were compared and their difference was small. The probe resister and inductance were compared with measurement result of a test PCB probe and they agreed well. Based on 2D model, a series of analysis was performed and basic design principles for PCB probes were obtained. Based on the principles, a new PCB probe with better performance was designed.

scholarly journals A plug-in electrophoresis microchip with PCB electrodes for contactless conductivity detection

2018 ◽  
Vol 5 (5) ◽  
pp. 171687 ◽  
Author(s):  
Mingpeng Yang ◽  
Zhe Huang ◽  
Hui You
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
Detection Performance ◽  
Circuit Board ◽  
Electrode Layer ◽  
Printed Circuit ◽  
Fabrication Cost ◽  
Portable Instruments ◽  
Electrophoresis Microchip ◽  
Train Of Thought

A plug-in electrophoresis microchip for large-scale use aimed at improving maintainability with low fabrication and maintenance costs is proposed in this paper. The plug-in microchip improves the maintainability of a device because the damaged microchannel layer can be changed without needing to cut off the circuit wires in the detection component. Obviously, the plug-in structure reduces waste compared with earlier microchips; at present the whole microchip has to be discarded, including the electrode layer and the microchannel layer. The fabrication cost was reduced as far as possible by adopting a steel template and printed circuit board electrodes that avoided the complex photolithography, metal deposition and sputtering processes. The detection performance of our microchip was assessed by electrophoresis experiments. The results showed an acceptable gradient and stable detection performance. The effect of the installation shift between the microchannel layer and the electrode layer brought about by the plug-in structure was also evaluated. The results indicated that, as long as the shift was controlled within a reasonable scope, its effect on the detection performance was acceptable. The plug-in microchip described in this paper represents a new train of thought for the large-scale use and design of portable instruments with electrophoresis microchips in the future.

Large-Scale Damage Path Simulation for Solder Joints in a BGA Package

2013 ◽  
Author(s):  
Takahiro Omori ◽  
Kenji Hirohata ◽  
Tomoko Monda ◽  
Minoru Mukai
Keyword(s):  
Crack Propagation ◽  
Life Prediction ◽  
Large Scale ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Electronic Packages ◽  
Printed Circuit ◽  
Bga Package ◽  
The Relationship

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.

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