Metallization of High Purity Al2O3 Substrate with Autocatalytic NiP Thin Films for Au Interconnections in MCM packaging technology.

A Multichip Module (MCM) is a structure consisting of several ICs (typically bare chips) interconnected on a common supporting substrate and packaged as a single device. In this packaging technology, gold (Au) thin films are used as interconnection tracks terminated by wire bonding process to the chips. Thus, the good quality of theses Au films (for interconnects purpose) is essential. The present work proposes a metallization sequence of high purity (99.9%) and polished Al2O3 substrates, with an autocatalytic (electroless) NiP thin film follow by an electrolytic Au film in order to improve the MCM interconnections quality. The results show NiP and Au films with good adhesion, low roughness, good thickness distribution and optimal electrical properties, which allows us to establish a methodology that guarantees the reproducibility and quality of the Au interconnections in MCM devices.

System Electrothermal Transient Analysis of a High Current (40A) Synchronous Step Down Converter

In this paper, we detailed the system electrothermal transient co-design modeling and silicon validation effort that led to the industry’s first highly efficient, highest power density (40A) synchronous step-down converter. The device was designed in an innovative multichip module (MCM) low-profile LQFN packaging technology. By integrating the control and drive circuitry with two discrete N-channel power MOSFETs, significant reduction in system on-resistance, RDS(ON), was achieved. The validity of the co-design electrothermal modeling methodology was assessed by comparing directly to silicon thermal measurements made on an evaluation module (EVM) which comprises the inductor, capacitor, and other essential components. Correlation between simulation and laboratory measurements on the integrated solution will be discussed.

Multichip Module Planarity Requirements Derived From Solder Surface Tension Models

The number of die and routing layers in multichip modules and fan-out packages has been steadily increasing, which has exasperated the problem of maintaining module planarity for interconnect to a system board. The usual remedies are to try to match coefficients of thermal expansion as closely as possible, balance composition of layers on either side of a module's neutral axis, and build on stiff, planar interposers. All of these strategies can affect module performance, size, and cost. We have examined an alternative approach to accommodating module bow, by allowing the solder ball interconnects to compress or elongate as necessary to maintain electrical connections. This approach is further enhanced by making the module very thin, which does not reduce its bow, but rather allows the high surface tension force exerted by molten solder to flatten the module. We have derived a model for the surface tension force exerted by a solder ball as a function of the degree to which it is compressed or elongated. This model also predicts the maximum elongation that the solder connection can sustain before it ruptures. We have applied this model in a design tool, which allows us to predict the maximum module bow that can be accommodated as a function of the number, size, and location of the solder connections and the physical composition of the multichip module.

Multichip Module Planarity Requirements Derived From Solder Surface Tension Models

The number of die and routing layers in multichip modules has been steadily increasing, which has exasperated the problem of maintaining module planarity for interconnect to a system board. The usual remedies are to try to balance the composition of the layers on either side of the module's neutral axis or to build the layers on a stiff, planar interposer. Both of these approaches can impact module performance, size and cost. We have examined an alternative approach to accommodating module bow, by allowing the solder ball interconnects to compress or elongate as necessary to maintain electrical connections. This approach is further enhanced by making the module very thin, which does not reduce its bow, but rather allows the high surface tension force exerted by molten solder to flatten the module. We have derived a model for the surface tension force exerted by a solder ball as a function of the degree to which it is compressed or elongated. This model also predicts the maximum elongation that the solder connection can sustain before it ruptures. We have applied this model in a design tool, which allows us to predict the maximum module bow that can be accommodated as a function of the number, size and location of the solder connections and the physical composition of the multichip module.