Abnormal Shear Performance of Microscale Ball Grid Array Structure Cu/Sn–3.0Ag–0.5Cu/Cu Solder Joints with Increasing Current Density

The shear performance and fracture behavior of microscale ball grid array structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with increasing electric current density (from 1.0 × 103 to 6.0 × 103 A/cm2) at various test temperatures (25 °C, 55 °C, 85 °C, 115 °C, 145 °C, and 175 °C) were investigated systematically. Shear strength increases initially, then decreases with increasing current density at a test temperature of no more than 85 °C; the enhancement effect of current stressing on shear strength decreases and finally diminishes with increasing test temperatures. These changes are mainly due to the counteraction of the athermal effect of current stressing and Joule heating. After decoupling and quantifying the contribution of the athermal effect to the shear strength of solder joints, the results show that the influence of the athermal effect presents a transition from an enhancement state to a deterioration state with increasing current density, and the critical current density for the transition decreases with increasing test temperatures. Joule heating is always in a deterioration state on the shear strength of solder joints, which gradually becomes the dominant factor with increasing test temperatures and current density. In addition, the fracture location changes from the solder matrix to the interface between the solder matrix and the intermetallic compound (IMC) layer (the solder/IMC layer interface) with increasing current density, showing a ductile-to-brittle transition. The interfacial fracture is triggered by current crowding at the groove of the IMC layer and driven by mismatch strain at the solder/IMC layer interface, and the critical current density for the occurrence of interfacial fracture decreases with increasing test temperatures.

Effect of high-frequency PCB laminate on thermal cycling behavior of electronic packaging structures

PurposeAs the solution to improve fatigue life and mechanical reliability of packaging structure, the material selection in PCB stack-up and partitioning design on PCB to eliminate the electromagnetic interference by keeping all circuit functions separate are suggested to be optimized from the mechanical stress point of view.Design/methodology/approachThe present paper investigated the effect of RO4350B and RT5880 printed circuit board (PCB) laminates on fatigue life of the QFN (quad flat no-lead) packaging structure for high-frequency applications. During accelerated thermal cycling between −50 °C and 100 °C, the mismatched coefficients of thermal expansion (CTE) between packaging and PCB materials, initial PCB warping deformation and locally concentrated stress states significantly affected the fatigue life of the packaging structure. The intermetallics layer and mechanical strength of solder joints were examined to ensure the satisfactorily soldering quality prior to the thermal cycling process. The failure mechanism was investigated by the metallographic observations using a scanning electron microscope.FindingsTypical fatigue behavior was revealed by grain coarsening due to cyclic stress, while at critical locations of packaging structures, the crack propagations were confirmed to be accompanied with coarsened grains by dye penetration tests. It is confirmed that the cyclic stress induced fatigue deformation is dominant in the deformation history of both PCB laminates. Due to the greater CTE differences in the RT5880 PCB laminate with those of the packaging materials, the thermally induced strains among different layered materials were more mismatched and led to the initiation and propagation of fatigue cracks in solder joints subjected to more severe stress states.Originality/valueIn addition to the electrical insulation and thermal dissipation, electronic packaging structures play a key role in mechanical connections between IC chips and PCB.

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

The Effect of Grain Orientation of β-Sn on Copper Pillar Solder Joints during Electromigration

The grain orientation of Sn-based solder joints on copper pillars under the combined action of electron wind force and temperature gradient greatly affects their electromigration damage. The copper pillars with Sn-1.8Ag lead-free solder on the top was subjected to a current density of 1.5 × 104 A/cm2 at 125 °C to study the electromigration behaviors. The grain orientation was characterized by scanning electron microscopy (SEM) equipped with electron backscattered diffraction (EBSD) detector. Metal dissolution and voids formation in the cathode as well as massive intermetallic compounds(IMC) accumulation in the anode were observed after electromigration. Closer examination of solder joints revealed that the Sn grain whose c-axis perpendicular to electric current may have retarded Cu diffusion to anode and IMC accumulation. In addition, the newly formed Cu6Sn5 exhibited preferred orientation related to the electric current direction.

Effect of Ni(P) Layer Thickness on Interface Reaction and Reliability of Ultrathin ENEPIG Surface Finish

Electroless Ni(P)/electroless Pd/immersion Au (ENEPIG) is a common surface finish in electronic packaging, while the Ni(P) layer increases the impedance of solder joints and leads to signal quality degradation in high-frequency circuits. Reducing the thickness of the Ni(P) layer can balance the high impedance and weldability. In this paper, the interfacial reaction process between ultrathin ENEPIG substrates with different Ni layer thicknesses (0.112 and 0.185 μm) and Sn–3.0Ag–0.5Cu (SAC305) solder during reflow and aging was studied. The bonding ability and reliability of solder joints with different surface finishes were evaluated based on solder ball shear test, drop test and temperature cycle test (TCT), and the failure mechanism was analyzed from the perspective of intermetallic compound (IMC) interface growth. The results showed that the Ni–Sn–P layer generated by ultrathin ENEPIG can inhibit the growth of brittle IMC so that the solder joints maintain high shear strength. Ultrathin ENEPIG with a Ni layer thickness of 0.185 μm had no failure cracks under thermal cycling and drop impact, which can meet actual reliability standards. Therefore, ultrathin ENEPIG has broad prospects and important significance in the field of high-frequency chip substrate design and manufacturing.

Effects of Isothermal Aging on Interfacial Microstructure and Shear Properties of Sn-4.5Sb-3.5Bi-0.1Ag Soldering with ENIG and ENEPIG Substrates

Sn–Sb system solders and ENIG/ENEPIG surface finish layers are commonly used in electronic products. To illustrate the thermal reliability evaluation of such solder joints, we studied the interfacial microstructure and shear properties of Sn-4.5Sb-3.5Bi-0.1Ag/ENIG and Sn-4.5Sb-3.5Bi-0.1Ag/ENEPIG solder joints after aging at 150 °C for 250, 500 and 1000 h. The results show that the intermetallic compound of Sn-4.5Sb-3.5Bi-0.1Ag/ENIG interface was more continuous and uniform compared with that of Sn-4.5Sb-3.5Bi-0.1Ag/ENEPIG interface after reflow. The thickness of the interfacial intermetallic compounds of the former was significantly thinner than that of the latter before and after aging. With extension of aging time, the former interface was stable, while obvious voids appeared at the interface of the latter after 500 h aging and significant fracture occurred after 1000 h aging. The shear tests proved that shear strength of solder joints decreased with increasing aging time. For the Sn-4.5Sb-3.5Bi-0.1Ag/ENEPIG joint after 1000 h aging, the fracture mode is ductile-brittle mixed type, which means fracture could occur at the solder matrix or the solder/IMC interface. For other samples of these two types of joints, ductile fracture occurred inside of the solder. The Sn-4.5Sb-3.5Bi-0.1Ag/ENIG solder joint was thermally more reliable than Sn-4.5Sb-3.5Bi-0.1Ag/ENEPIG.